ShiboSoftwareDev/nema8-20mm-dual-usbc-stepper-controller
A compact 20 mm four-layer USB‑C stepper-controller PCB combining CH32X035 MCU control, TMC2209 motor driving, USB‑C PD/data interfaces, protection/power regulation, temperature/LED status hardware, and NEMA8 motor connectivity.
- Version
- 1.0.34
- License
- unset
- Stars
- 0
index.circuit.tsx
PCB
Schematic
import { Fragment } from "react"
import { assembly } from "tscircuit"
import { AutoroutingPipelineSolver9_PreloadedTraceGraph } from "@tscircuit/capacity-autorouter"
import releaseV1011AutorouterTraces from "./routes/release-v1.0.11-autorouter-traces.json"
import { BAT54KFILM } from "./imports/BAT54KFILM"
import { BAT54WS } from "./imports/BAT54WS"
import { BM04B_SRSS_TB_LF__SN_ } from "./imports/BM04B_SRSS_TB_LF__SN_"
import { BSMD1206_110_16V } from "./imports/BSMD1206_110_16V"
import { CH32X035F8U6_ALT } from "./imports/CH32X035F8U6_ALT"
import { USB4145_03_0070_C } from "./imports/USB4145_03_0070_C"
import { HT7533_1 } from "./imports/HT7533_1"
import { PMEG6020ELRX } from "./imports/PMEG6020ELRX"
import { SMAJ16A } from "./imports/SMAJ16A"
import { PT1206FR_7W0R33L } from "./imports/PT1206FR_7W0R33L"
import { TMC2209_LA_T } from "./imports/TMC2209_LA_T"
import { TL3780AF100QG } from "./imports/TL3780AF100QG"
import { TMP102AIDRLR } from "./imports/TMP102AIDRLR"
import { USBLC6_2SC6 } from "./imports/USBLC6_2SC6"
import { WS2812B_1313_V6 } from "./imports/WS2812B_1313_V6"
const resistorParts: Record<string, string> = {
"27": "C25100",
"1k": "C11702",
"4.7k": "C25900",
"5.1k": "C25905",
"10k": "C25744",
"12k": "C25752",
"47k": "C25792",
"100k": "C25741",
"270k": "C25770",
}
const capacitorParts: Record<string, { part: string; footprint: string; voltage: string }> = {
"22nF_50V": { part: "C1532", footprint: "0402", voltage: "50V" },
"100nF": { part: "C1525", footprint: "0402", voltage: "16V" },
"100nF_50V": { part: "C14663", footprint: "0603", voltage: "50V" },
"100nF_50V_0402": { part: "C525226", footprint: "0402", voltage: "50V" },
"2.2uF_10V": { part: "C107370", footprint: "0402", voltage: "10V" },
"2.2uF_25V_0402": { part: "C6119765", footprint: "0402", voltage: "25V" },
"2.2uF": { part: "C23630", footprint: "0603", voltage: "16V" },
"10uF_25V": { part: "C96446", footprint: "0603", voltage: "25V" },
"47uF_25V": { part: "C50767273", footprint: "1206", voltage: "25V" },
}
const R = ({ name, resistance, connections: _connections, ...props }: any) => (
<resistor
name={name}
resistance={resistance}
footprint="0402"
supplierPartNumbers={{ jlcpcb: [resistorParts[resistance]] }}
{...props}
/>
)
const C = ({ name, value, connections: _connections, ...props }: any) => {
const item = capacitorParts[value]
return (
<capacitor
name={name}
capacitance={value.replace(/_\d+V$/, "")}
footprint={item.footprint}
maxVoltageRating={item.voltage}
maxDecouplingTraceLength="50mm"
supplierPartNumbers={{ jlcpcb: [item.part] }}
{...props}
/>
)
}
const R0201 = ({ name, resistance, ...props }: any) => (
<resistor
name={name}
resistance={resistance}
footprint="0201"
supplierPartNumbers={{ jlcpcb: ["C170207"] }}
{...props}
/>
)
const C0201 = ({ name, ...props }: any) => (
<capacitor
name={name}
capacitance="100nF"
footprint="0201"
maxVoltageRating="16V"
maxDecouplingTraceLength="50mm"
supplierPartNumbers={{ jlcpcb: ["C18164586"] }}
{...props}
/>
)
const C1uF0201 = ({ name, ...props }: any) => (
<capacitor
name={name}
capacitance="1uF"
footprint="0201"
maxVoltageRating="10V"
maxDecouplingTraceLength="50mm"
supplierPartNumbers={{ jlcpcb: ["C48986257"] }}
{...props}
/>
)
const nets = [
"GND",
"PD_VBUS_RAW",
"PD_VBUS_FUSED",
"VM",
"USB_5V",
"LOGIC_IN",
"VIO",
"PD_CC1",
"PD_CC2",
"DATA_CC1",
"DATA_CC2",
"USB_DM_CONN",
"USB_DP_CONN",
"USB_DM",
"USB_DP",
"BOOT_BIAS",
"VBUS_ADC",
"DIAG",
"STEP",
"DIR",
"ENN",
"STDBY",
"UART_MCU",
"UART_DRV",
"V5_DRV",
"VREF",
"CP_HI",
"CP_LO",
"VCP",
"SENSE_A",
"SENSE_B",
"MOTOR_A_POS",
"MOTOR_A_NEG",
"MOTOR_B_POS",
"MOTOR_B_NEG",
"TEMP_SCL",
"TEMP_SDA",
"STATUS_LED",
] as const
const sheets = {
power: "power",
control: "control",
driver: "driver",
} as const
const sections = {
pdInput: "pd_input",
logicPower: "logic_power",
usbData: "usb_data",
controller: "controller",
driverCore: "driver_core",
} as const
const driverX = 0
const driverY = -0.5
const mcuX = 5.6
const mcuY = 0
const thermalViaOffsets = [
[-0.7, -0.7], [-0.7, 0.7], [0.7, -0.7], [0.7, 0.7],
] as const
const motorMountingHoles = [
{ name: "MOTOR_M2_UPPER_LEFT", x: -7.7, y: 7.7 },
{ name: "MOTOR_M2_UPPER_RIGHT", x: 7.7, y: 7.7 },
{ name: "MOTOR_M2_LOWER_LEFT", x: -7.7, y: -7.7 },
{ name: "MOTOR_M2_LOWER_RIGHT", x: 7.7, y: -7.7 },
] as const
// Placement-only mechanical courtyard for the M2 rear screw heads. The
// 2.35 mm radius covers the 2.0 mm nominal head radius, 0.10 mm radial play
// in the 2.2 mm PCB hole, and the motor drawing's +/-0.15 mm hole-pattern
// tolerance. This is deliberately a courtyard, not a copper keepout.
const motorMountingClearanceRadius = 2.35
const MotorMountingHole = ({ name, x, y }: { name: string; x: number; y: number }) => (
<chip
name={name}
pcbX={x}
pcbY={y}
noSchematicRepresentation
doNotPlace
footprint={
<footprint>
<hole diameter="2.2mm" />
<courtyardcircle radius={`${motorMountingClearanceRadius}mm`} />
</footprint>
}
/>
)
// StepperOnline 8HS15-0604S mechanical envelope from drawing A1733.
// The rear screw pattern is shown so the assembly preview includes the
// hardware that the PCB standoffs must clear. The JST-SH-4 motor termination
// is rotated to the board's left edge so assembly.cable can model the harness
// to J_MOTOR without crossing the motor or PCB.
const motorModel = [
"nema8",
"bodywidth20.3mm",
"bodylength39.3mm",
"holespacing15.4mm",
"holediameter2mm",
"holedepth2.5mm",
"shaftlength10mm",
"shaftdiameter4mm",
"dshaft",
"flatdepth0.5mm",
"flatlength7mm",
"backfacescrews",
"backholespacing15.4mm",
"backholediameter2mm",
"backholedepth2.5mm",
"backscrewm2",
"jstsh4",
"wireangle0deg",
].join("_")
const motorToBoardMountGap = "4mm"
const verticalUsbShellPaths = [
{ pin: "GND1", x: -3.8475, y: 1.4299 },
{ pin: "GND2", x: 4.1525, y: 1.4299 },
{ pin: "GND3", x: -3.8475, y: -1.4299 },
{ pin: "GND4", x: 4.1525, y: -1.4299 },
] as const
const traceWidthForNet = (name: (typeof nets)[number]) => {
if (name === "MOTOR_A_POS") return "0.45mm"
if (name.startsWith("MOTOR_")) return "0.3mm"
if (name.startsWith("SENSE_")) return "0.3mm"
if (name === "PD_VBUS_RAW" || name === "PD_VBUS_FUSED") return "0.5mm"
if (name === "VM") return "0.56mm"
if (["USB_5V", "LOGIC_IN", "VIO", "V5_DRV", "VCP"].includes(name)) return "0.25mm"
return "0.15mm"
}
// Ground is carried by a dedicated inner-1 plane. Every outer-layer ground
// land gets a full-stack 0.30/0.45 mm through-via fanout into that plane.
const driverEpGroundPaths = [
{ from: ".U_DRV > .GND2", path: [
{ x: -0.5, y: -1.3 },
{ x: 0, y: 0 },
] },
{ from: ".U_DRV > .GND1", path: [
{ x: 0, y: 1.3 },
{ x: 0, y: 0 },
] },
{ from: ".U_DRV > .SPREAD", path: [
{ x: 1.6, y: -2.5 }, { x: 1.6, y: -1.4 }, { x: 0, y: 0 },
] },
{ from: ".U_DRV > .MS1_AD0", path: [
{ x: 1.4, y: -1.0 }, { x: 0, y: 0 },
] },
{ from: ".U_DRV > .MS2_AD1", path: [
{ x: 1.4, y: -0.5 }, { x: 0, y: 0 },
] },
{ from: ".U_DRV > .CLK", path: [
{ x: 1.4, y: 1.0 }, { x: 0, y: 0 },
] },
{ from: ".U_DRV > .UNUSED", path: [
{ x: -1.4, y: 0 }, { x: 0, y: 0 },
] },
] as const
const groundFanouts = [
// Coordinates are local to each source component (the pcbPath convention).
{ from: ".C_VM_HF1 > .pin2", x: 1.4, y: 0, fromLayer: "top" },
{ from: ".C_VM_BULK1 > .pin2", x: -1.33, y: -0.6, fromLayer: "bottom" },
{ from: ".C_VM_BULK2 > .pin2", x: -1.0, y: 1.2, fromLayer: "bottom" },
{ from: ".R_PD_CC1 > .pin2", x: -1.1, y: 0, fromLayer: "bottom" },
{ from: ".R_PD_CC2 > .pin2", x: -1.1, y: 0, fromLayer: "bottom" },
{ from: ".R_DATA_CC1 > .pin2", x: -0.51, y: 0.65, fromLayer: "bottom" },
{ from: ".R_DATA_CC2 > .pin2", x: -0.51, y: -0.65, fromLayer: "bottom" },
{ from: ".U_3V3 > .GND", x: -0.3, y: -1.0, fromLayer: "bottom" },
{ from: ".C_3V3_BULK > .pin2", x: -0.4, y: 0.6, fromLayer: "bottom" },
{ from: ".C_MCU_HF > .pin2", x: -0.1, y: 0.3, fromLayer: "bottom" },
{ from: ".C_MCU_BULK > .pin2", x: -0.5, y: 0.2, fromLayer: "bottom" },
{ from: ".R_STDBY_PD > .pin2", x: 1.1, y: 0, fromLayer: "top" },
{ from: ".R_VREF_BOTTOM > .pin2", x: -0.7, y: 0.8, fromLayer: "bottom" },
{ from: ".R_VBUS_BOTTOM > .pin2", x: 0.8, y: 0, fromLayer: "top" },
{ from: ".R_SENSE_A > .pin2", x: -2.2, y: 0, fromLayer: "bottom" },
{ from: ".R_SENSE_B > .pin2", x: -2.0, y: 1.0, fromLayer: "bottom" },
] as const
// Explicitly enumerate the signal/power routes so the default autorouter does
// not waste channels trying to duplicate the copper-pour ground network.
const routedConnections = [
[".J_USB_PD > .VBUS1", ".F1 > .pin1"],
[".J_USB_PD > .VBUS2", ".F1 > .pin1"],
[".F1 > .pin2", ".D_BLOCK > .anode"],
[".D_BLOCK > .cathode", ".D_VM_TVS > .cathode"],
[".D_VM_TVS > .cathode", ".C_VM_BULK1 > .pin1"],
[".C_VM_BULK1 > .pin1", ".C_VM_BULK2 > .pin1"],
[".C_VM_BULK2 > .pin1", ".D_LOGIC_PD > .anode"],
[".D_LOGIC_PD > .anode", ".R_VBUS_TOP > .pin1"],
[".D_LOGIC_PD > .anode", ".C_VM_HF1 > .pin1"],
[".C_VM_HF1 > .pin1", ".U_DRV > .VS1"],
[".U_DRV > .VS1", ".U_DRV > .VS2"],
[".C_VM_HF1 > .pin1", ".C_VCP > .pin2"],
[".J_USB_DATA > .VBUS1", ".D_LOGIC_USB > .anode"],
[".J_USB_DATA > .VBUS2", ".D_LOGIC_USB > .anode"],
[".D_LOGIC_PD > .cathode", ".D_LOGIC_USB > .cathode"],
[".D_LOGIC_USB > .cathode", ".U_3V3 > .VIN"],
[".U_3V3 > .VIN", ".C_LDO_IN > .pin1"],
[".U_3V3 > .VOUT", ".C_3V3_BULK > .pin1"],
[".C_3V3_BULK > .pin1", ".U_MCU > .VDD"],
[".U_MCU > .VDD", ".C_MCU_HF > .pin1"],
[".C_MCU_HF > .pin1", ".C_MCU_BULK > .pin1"],
[".C_MCU_HF > .pin1", ".R_BOOT > .pin1"],
[".C_MCU_BULK > .pin1", ".R_EN_PU > .pin1"],
[".R_EN_PU > .pin1", ".U_DRV > .VCC_IO"],
[".U_DRV > .VCC_IO", ".C_VIO > .pin1"],
[".U_DRV > .VCC_IO", ".U_USB_ESD > .VBUS"],
[".J_USB_PD > .CC1", ".U_MCU > .CC1"],
[".J_USB_PD > .CC2", ".U_MCU > .CC2"],
[".J_USB_DATA > .CC1", ".R_DATA_CC1 > .pin1"],
[".J_USB_DATA > .CC2", ".R_DATA_CC2 > .pin1"],
[".J_USB_DATA > .DN1", ".U_USB_ESD > .DM_IN"],
[".J_USB_DATA > .DN2", ".U_USB_ESD > .DM_IN"],
[".J_USB_DATA > .DP1", ".U_USB_ESD > .DP_IN"],
[".J_USB_DATA > .DP2", ".U_USB_ESD > .DP_IN"],
[".U_USB_ESD > .DM_OUT", ".U_MCU > .USB_DM"],
[".U_USB_ESD > .DP_OUT", ".U_MCU > .USB_DP"],
[".U_MCU > .USB_DP", ".SW_BOOT > .pin102"],
[".R_BOOT > .pin2", ".SW_BOOT > .pin101"],
[".R_VBUS_TOP > .pin2", ".R_VBUS_BOTTOM > .pin1"],
[".R_VBUS_BOTTOM > .pin1", ".U_MCU > .VBUS_ADC"],
[".U_DRV > .DIAG", ".U_MCU > .DIAG_IN"],
[".U_DRV > .STEP", ".U_MCU > .STEP_OUT"],
[".U_DRV > .DIR", ".U_MCU > .DIR_OUT"],
[".R_EN_PU > .pin2", ".U_MCU > .ENABLE_OUT"],
[".U_DRV > .ENN", ".R_EN_PU > .pin2"],
[".U_DRV > .STDBY", ".U_MCU > .STDBY_OUT"],
[".U_DRV > .STDBY", ".R_STDBY_PD > .pin1"],
[".U_MCU > .UART1", ".U_DRV > .PDN_UART"],
[".U_MCU > .UART1", ".U_DRV > .PDN_UART"], // reserved duplicate; not rendered
[".U_DRV > .5VOUT", ".C_5V > .pin1"],
[".C_5V > .pin1", ".R_VREF_TOP > .pin1"],
[".R_VREF_TOP > .pin2", ".R_VREF_BOTTOM > .pin1"],
[".R_VREF_BOTTOM > .pin1", ".C_VREF > .pin1"],
[".C_VREF > .pin1", ".U_DRV > .VREF"],
[".U_DRV > .CPO", ".C_CP > .pin1"],
[".U_DRV > .CPI", ".C_CP > .pin2"],
[".U_DRV > .VCP", ".C_VCP > .pin1"],
[".U_DRV > .BRA", ".R_SENSE_A > .pin1"],
[".U_DRV > .BRB", ".R_SENSE_B > .pin1"],
[".U_DRV > .OA2", ".J_MOTOR > .pin1"],
[".U_DRV > .OA1", ".J_MOTOR > .pin2"],
[".U_DRV > .OB1", ".J_MOTOR > .pin3"],
[".U_DRV > .OB2", ".J_MOTOR > .pin4"],
[".C_VM_HF1 > .pin2", ".U_DRV > .GND1"],
[".D_VM_TVS > .anode", ".C_VM_BULK1 > .pin2"],
[".D_VM_TVS > .anode", ".C_VM_BULK2 > .pin2"],
[".U_DRV > .SPREAD", ".U_DRV > .EP"],
[".U_DRV > .MS1_AD0", ".U_DRV > .EP"],
[".U_DRV > .MS2_AD1", ".U_DRV > .EP"],
[".U_DRV > .CLK", ".U_DRV > .EP"],
[".U_DRV > .UNUSED", ".U_DRV > .EP"],
[".R_DATA_CC1 > .pin2", ".R_DATA_CC2 > .pin2"],
[".R_DATA_CC2 > .pin2", ".U_MCU > .GND"],
[".U_USB_ESD > .GND", ".J_USB_DATA > .GND1"],
[".C_LDO_IN > .pin2", ".U_3V3 > .GND"],
[".C_3V3_BULK > .pin2", ".C_LDO_IN > .pin2"],
[".U_3V3 > .GND", ".J_USB_DATA > .EH3"],
[".C_MCU_HF > .pin2", ".U_MCU > .GND"],
[".C_MCU_BULK > .pin2", ".U_MCU > .GND"],
[".R_STDBY_PD > .pin2", ".U_DRV > .EP"],
[".C_5V > .pin2", ".U_DRV > .EP"],
[".C_VIO > .pin2", ".U_DRV > .EP"],
[".R_VREF_BOTTOM > .pin2", ".U_DRV > .EP"],
[".C_VREF > .pin2", ".U_DRV > .EP"],
[".R_VBUS_BOTTOM > .pin2", ".U_MCU > .GND"],
[".C_VM_BULK1 > .pin2", ".J_USB_PD > .GND1"],
[".C_VM_BULK2 > .pin2", ".J_USB_PD > .GND2"],
[".R_SENSE_A > .pin2", ".U_DRV > .EP"],
[".R_SENSE_B > .pin2", ".U_DRV > .EP"],
] as const
// ROUTE_n remains the internal PCB routing identity because the router and bus
// policies depend on it. The schematic deliberately shows the electrical net
// name instead, matching the readable-label pattern used by the reference
// stepper-controller designs.
const routeSchematicLabels = [
"PD_VBUS_RAW", "PD_VBUS_RAW", "PD_VBUS_FUSED",
"VM", "VM", "VM", "VM", "VM", "VM", "VM", "VM", "VM",
"USB_5V", "USB_5V", "LOGIC_IN", "LOGIC_IN", "LOGIC_IN",
"VIO", "VIO", "VIO", "VIO", "VIO", "VIO", "VIO", "VIO", "VIO",
"PD_CC1", "PD_CC2", "DATA_CC1", "DATA_CC2",
"USB_DM_CONN", "USB_DM_CONN", "USB_DP_CONN", "USB_DP_CONN",
"USB_DM", "USB_DP", "USB_DP", "BOOT_BIAS",
"VBUS_ADC", "VBUS_ADC", "DIAG", "STEP", "DIR", "ENN", "ENN",
"STDBY", "STDBY", "UART", "UART",
"V5_DRV", "V5_DRV", "VREF", "VREF", "VREF",
"CP_HI", "CP_LO", "VCP", "SENSE_A", "SENSE_B",
"MOTOR_A_POS", "MOTOR_A_NEG", "MOTOR_B_POS", "MOTOR_B_NEG",
"GND", "GND", "GND", "GND", "GND", "GND", "GND", "GND", "GND",
"GND", "GND", "GND", "GND", "GND", "GND", "GND", "GND", "GND",
"GND", "GND", "GND", "GND", "GND", "GND", "GND", "GND",
] as const
// These are the actual source/PCB trace identifiers shown by the PCB
// inspector. Keep them unique, but make every name describe the same
// electrical function shown by routeSchematicLabels above.
const routeTraceNames = [
"PD_VBUS1_TO_FUSE", "PD_VBUS2_TO_FUSE", "PD_VBUS_FUSED_TO_BLOCK",
"VM_BLOCK_TO_TVS", "VM_TVS_TO_BULK1", "VM_BULK1_TO_BULK2",
"VM_BULK2_TO_LOGIC_DIODE", "VM_TO_ADC_DIVIDER", "VM_TO_DRIVER_BYPASS",
"VM_BYPASS_TO_DRIVER_VS1", "VM_DRIVER_VS1_TO_VS2", "VM_TO_VCP_CAP",
"USB_5V_VBUS1_TO_OR_DIODE", "USB_5V_VBUS2_TO_OR_DIODE",
"LOGIC_IN_PD_OR_TO_USB_OR", "LOGIC_IN_OR_TO_LDO", "LOGIC_IN_LDO_BYPASS",
"VIO_LDO_TO_BULK", "VIO_BULK_TO_MCU", "VIO_MCU_TO_HF_CAP",
"VIO_HF_TO_MCU_BULK", "VIO_TO_BOOT_PULLUP", "VIO_TO_ENABLE_PULLUP",
"VIO_ENABLE_PULLUP_TO_DRIVER", "VIO_DRIVER_TO_BYPASS", "VIO_DRIVER_TO_USB_ESD",
"PD_CC1_TO_MCU", "PD_CC2_TO_MCU", "DATA_CC1_TO_RD", "DATA_CC2_TO_RD",
"USB_DM1_TO_ESD", "USB_DM2_TO_ESD", "USB_DP1_TO_ESD", "USB_DP2_TO_ESD",
"USB_DM_ESD_TO_MCU", "USB_DP_ESD_TO_MCU", "USB_DP_TO_BOOT_SWITCH",
"BOOT_BIAS_TO_SWITCH", "VBUS_ADC_DIVIDER", "VBUS_ADC_TO_MCU",
"DIAG_DRIVER_TO_MCU", "STEP_DRIVER_TO_MCU", "DIR_DRIVER_TO_MCU",
"ENN_PULLUP_TO_MCU", "ENN_DRIVER_TO_PULLUP", "STDBY_DRIVER_TO_MCU",
"STDBY_DRIVER_TO_PULLDOWN", "UART_MCU_TO_DRIVER", "UART_RESERVED_DUPLICATE",
"V5_DRV_TO_BYPASS", "V5_DRV_TO_VREF_TOP", "VREF_DIVIDER",
"VREF_DIVIDER_TO_CAP", "VREF_CAP_TO_DRIVER", "CP_HI_DRIVER_TO_CAP",
"CP_LO_DRIVER_TO_CAP", "VCP_DRIVER_TO_CAP", "SENSE_A_DRIVER_TO_RESISTOR",
"SENSE_B_DRIVER_TO_RESISTOR", "MOTOR_A_POS_DRIVER_TO_JST",
"MOTOR_A_NEG_DRIVER_TO_JST", "MOTOR_B_POS_DRIVER_TO_JST",
"MOTOR_B_NEG_DRIVER_TO_JST",
] as const
const traceWidthForRouteIndex = (index: number) => {
if (index <= 2) return "0.5mm"
if (index <= 11) return "0.56mm"
if (index >= 57 && index <= 58) return "0.3mm"
if (index === 59) return "0.45mm"
if (index >= 60 && index <= 62) return "0.3mm"
if (index === 63) return "0.3mm"
if (index === 64 || index === 65) return "0.5mm"
if (index >= 71 && index <= 73) return "0.2mm"
if (index >= 74 && index <= 76) return "0.25mm"
if (index >= 77 && index <= 83) return "0.2mm"
if (index === 84) return "0.2mm"
if (index === 85 || index === 86) return "0.5mm"
if (index === 87 || index === 88) return "0.3mm"
if ((index >= 12 && index <= 25) || index === 49 || index === 50 || index === 56) return "0.25mm"
if (index === 54 || index === 55) return "0.2mm"
return "0.15mm"
}
const routeNames = (start: number, end: number) =>
routeTraceNames.slice(start, end + 1)
const autoroutedRouteNames = (start: number, end: number) =>
Array.from({ length: end - start + 1 }, (_, offset) => start + offset)
.filter((index) => !manualRouteIndexes.has(index))
.map((index) => routeTraceNames[index])
// Keep signal and power nets under the default autorouter. This avoids the
// partial-layer via definitions that hand routing can accidentally introduce;
// every layer transition is generated as a normal plated through-via.
const manualRouteIndexes = new Set<number>([51])
const manualPcbPathForRouteIndex = (index: number): any[] | undefined => {
if (index === 14) return [
{ x: 0.8, y: 1.6 },
{ x: 4.6, y: 1.6 },
{ x: 4.6, y: 0.6 },
{ x: 4.34, y: 0.6 },
]
if (index === 15) return [
{ x: 1.14, y: 0 },
{ x: 0.2, y: 0.5 },
{ x: 0.2, y: 10.5 },
{ x: 1.1, y: 10.5 },
{ x: 1.1, y: 12.6 },
{ x: 0.63, y: 12.6 },
]
if (index === 16) return [
{ x: 1.23, y: 0 },
{ x: 1.6, y: -1.0 },
{ x: 1.6, y: -2.975 },
]
if (index === 24) return [
{ x: 1.8, y: 2.5 },
{ x: 3.2, y: 2.3 },
]
if (index === 26) return [
{ x: -0.55, y: 1.2 },
{ x: -0.55, y: 1.2, via: true, fromLayer: "top", toLayer: "inner2" },
{ x: -0.55, y: 1.2 },
{ x: 5.4, y: 1.2 },
{ x: 4.7, y: 4.2 },
{ x: 4.7, y: 4.2, via: true, fromLayer: "inner2", toLayer: "bottom" },
{ x: 4.7, y: 4.2 },
{ x: 4.9, y: 4.6 },
]
if (index === 27) return [
{ x: 0.55, y: 1.2 },
{ x: 0.55, y: 1.2, via: true, fromLayer: "top", toLayer: "inner1" },
{ x: 0.55, y: 1.2 },
{ x: 0.55, y: 4.7 },
{ x: 4.0, y: 4.7 },
{ x: 4.0, y: 4.7, via: true, fromLayer: "inner1", toLayer: "bottom" },
{ x: 4.0, y: 4.7 },
{ x: 4.5, y: 5.0 },
]
if (index === 28) return [
{ x: -0.5975668, y: 1.479931 },
{ x: -0.5975668, y: 0.6 },
{ x: -2.4, y: 0.6 },
{ x: -2.4, y: 0.6, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: -2.4, y: 0.6 },
{ x: -1.7, y: 0.51 },
]
if (index === 29) return [
{ x: 0.9025572, y: -1.479931 },
{ x: 0.9025572, y: -0.7 },
{ x: 2.4, y: -0.7 },
{ x: 2.4, y: -0.7, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: 2.4, y: -0.7 },
{ x: 1.7, y: 0.51 },
]
if (index === 30) return [
{ x: 0.4024312, y: 1.479931 },
{ x: 0.8, y: 0.9 },
{ x: 1.4, y: 0.4 },
{ x: 1.4, y: 0.4, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: 1.4, y: 0.4 },
{ x: 0.95, y: -1.1491 },
]
if (index === 31) return [
{ x: -0.0974408, y: -1.479931 },
{ x: -0.0974408, y: -2.1 },
{ x: 1.4, y: -2.2 },
{ x: 1.4, y: -2.2, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: 1.4, y: -2.2 },
{ x: 0.95, y: -1.1491 },
]
if (index === 32) return [
{ x: -0.0974408, y: 1.479931 },
{ x: -0.8, y: 0.9 },
{ x: -1.4, y: 0.4 },
{ x: -1.4, y: 0.4, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: -1.4, y: 0.4 },
{ x: -0.95, y: -1.1491 },
]
if (index === 33) return [
{ x: 0.4024312, y: -1.479931 },
{ x: 0.4024312, y: -2.1 },
{ x: -1.4, y: -2.2 },
{ x: -1.4, y: -2.2, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: -1.4, y: -2.2 },
{ x: -0.95, y: -1.1491 },
]
if (index === 34) return [
{ x: 1.0, y: -2.4 },
{ x: 1.0, y: -2.4, via: true, fromLayer: "bottom", toLayer: "inner2" },
{ x: 1.0, y: -2.4 },
{ x: 1.0, y: -5.6 },
{ x: -1.2, y: -7.8 },
{ x: -7.3, y: -7.8 },
{ x: -7.3, y: -7.8, via: true, fromLayer: "inner2", toLayer: "bottom" },
{ x: -7.3, y: -7.8 },
{ x: -7.3, y: -5.0 },
{ x: -7.0, y: -4.5 },
]
if (index === 36) return [
{ x: 0, y: 2.3 },
{ x: 0, y: 2.3, via: true, fromLayer: "bottom", toLayer: "inner1" },
{ x: 0, y: 2.3 },
{ x: -2.7, y: 2.3 },
{ x: -2.7, y: -5.5 },
{ x: -3.2, y: -5.5 },
{ x: -3.2, y: -5.5, via: true, fromLayer: "inner1", toLayer: "top" },
{ x: -3.2, y: -5.5 },
]
if (index === 39) return [
{ x: 0.8, y: 1.0 },
{ x: 0.8, y: 1.0, via: true, fromLayer: "top", toLayer: "inner2" },
{ x: 0.8, y: 1.0 },
{ x: -2.6, y: 6.7 },
{ x: -2.6, y: 6.7, via: true, fromLayer: "inner2", toLayer: "bottom" },
{ x: -2.6, y: 6.7 },
]
if (index === 41) return [
{ x: 1.0, y: 3.3 },
{ x: 1.0, y: 3.3, via: true, fromLayer: "top", toLayer: "inner2" },
{ x: 1.0, y: 3.3 },
{ x: 1.5, y: 2.3 },
{ x: 1.5, y: -0.5 },
{ x: 3.2, y: -0.7 },
{ x: 3.2, y: -0.7, via: true, fromLayer: "inner2", toLayer: "bottom" },
{ x: 3.2, y: -0.7 },
{ x: 3.2, y: 0.1 },
]
if (index === 42) return [
{ x: -0.5, y: 2.5 },
{ x: -0.5, y: 3.3 },
{ x: 3.2, y: 3.3 },
{ x: 3.2, y: 3.3, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: 3.2, y: 0.5 },
{ x: 3.8, y: 0.5 },
]
if (index === 43) return [
{ x: -1.0, y: -3.2 },
{ x: -1.0, y: -3.2, via: true, fromLayer: "top", toLayer: "inner2" },
{ x: -1.0, y: -3.2 },
{ x: 3.5, y: -3.2 },
{ x: 3.5, y: 0.7 },
{ x: 3.7, y: 0.7 },
{ x: 3.7, y: 0.7, via: true, fromLayer: "inner2", toLayer: "bottom" },
{ x: 3.7, y: 0.7 },
]
if (index === 44) return [
{ x: -0.8, y: -3.2 },
{ x: -3.6, y: -3.2 },
]
if (index === 45) return [
{ x: -1.0, y: 3.3 },
{ x: -2.2, y: 3.3 },
{ x: -2.2, y: 3.3, via: true, fromLayer: "top", toLayer: "inner2" },
{ x: -2.2, y: 3.3 },
{ x: -2.2, y: 3.7 },
{ x: 3.1, y: 3.7 },
{ x: 3.1, y: 3.2 },
{ x: 3.1, y: 3.2, via: true, fromLayer: "inner2", toLayer: "bottom" },
{ x: 3.1, y: 3.2 },
{ x: 3.1, y: 2.5 },
{ x: 4.5, y: 2.5 },
{ x: 4.5, y: 2.0 },
]
if (index === 46) return [
{ x: -1.0, y: 3.0 },
{ x: -4.7, y: 2.7 },
]
if (index === 47) return [
{ x: 2.1, y: -0.8 },
{ x: 2.1, y: -1.2 },
{ x: 2.1, y: -1.2, via: true, fromLayer: "bottom", toLayer: "top" },
{ x: 2.1, y: -1.2 },
]
if (index === 49) return [
{ x: 3.0, y: -1.5 },
{ x: 3.5, y: -2.5 },
]
if (index === 50) return [
{ x: 0, y: -0.9 },
{ x: 0, y: -0.9, via: true, fromLayer: "top", toLayer: "inner1" },
{ x: 0, y: -0.9 },
{ x: 0, y: -0.6 },
{ x: -4.1, y: -0.6 },
{ x: -4.1, y: 0.6 },
{ x: -4.1, y: 0.6, via: true, fromLayer: "inner1", toLayer: "bottom" },
{ x: -4.1, y: 0.6 },
{ x: -4.1, y: 1.61 },
]
if (index === 51) return [
{ x: -0.51, y: 0 },
{ x: -0.51, y: -0.8 },
{ x: 2.81, y: -0.8 },
{ x: 2.81, y: 0 },
]
if (index === 52) return [
{ x: 0.51, y: -0.7 },
{ x: 2.81, y: -0.7 },
]
if (index === 53) return [
{ x: 0.2, y: 0 },
{ x: 0.2, y: 1.3 },
{ x: 0.2, y: 1.3, via: true, fromLayer: "bottom", toLayer: "top" },
{ x: 0.2, y: 1.3 },
]
if (index === 54) return [{ x: 0, y: -3.2 }]
if (index === 55) return [{ x: 0.5, y: -3.2 }]
if (index === 56) return [
{ x: 1.0, y: -3.1 },
{ x: 1.5, y: -3.3 },
{ x: 2.19, y: -3.3 },
]
if (index === 59) return [
{ x: -2.0, y: 2.0 },
{ x: -8.3, y: 2.0 },
]
if (index === 60) return [
{ x: -3.0, y: 0.5 },
{ x: -3.5, y: 1.0 },
{ x: -8.3, y: 1.0 },
]
if (index === 61) return [
{ x: -3.0, y: -0.5 },
{ x: -3.5, y: 0 },
{ x: -8.3, y: 0 },
]
if (index === 62) return [
{ x: -2.5, y: -1.5 },
{ x: -6.8, y: -1.5 },
{ x: -8.3, y: -1.0 },
]
if (index === 57) return [
{ x: -2.2, y: 1.0 },
{ x: -2.2, y: 1.0, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: -2.2, y: 1.0 },
]
if (index === 58) return [
{ x: -2.2, y: -1.0 },
{ x: -2.2, y: -1.0, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: -2.2, y: -1.0 },
]
return undefined
}
const routePhaseForIndex = (index: number) => {
if (index === 40 || manualRouteIndexes.has(index)) return null
return 1
}
const replaceAutoroutedRoute = (trace: any, route: any[]) => {
const original = trace.route ?? []
const firstPort = original.find((point: any) => point.start_pcb_port_id)?.start_pcb_port_id
const lastPort = [...original].reverse().find((point: any) => point.end_pcb_port_id)?.end_pcb_port_id
return {
...trace,
route: route.map((point, index) => ({
...point,
...(index === 0 && firstPort ? { start_pcb_port_id: firstPort } : {}),
...(index === route.length - 1 && lastPort ? { end_pcb_port_id: lastPort } : {}),
})),
}
}
const postprocessDenseUsbRoutes = (traces: any[]) => traces.map((trace: any) => {
const traceIdentity = `${trace.connection_name ?? ""} ${trace.pcb_trace_id ?? ""}`
const route = trace.route ?? []
const touches = (x: number, y: number) => route.some((point: any) =>
Math.abs((point.x ?? Infinity) - x) < 0.01 && Math.abs((point.y ?? Infinity) - y) < 0.01)
if (traceIdentity.includes("DATA_CC1_TO_RD") || touches(-0.69, 8.6)) {
return replaceAutoroutedRoute(trace, [
{ route_type: "wire", x: 2.4, y: 3.876, width: 0.15, layer: "top" },
{ route_type: "wire", x: 2.4, y: 3.0, width: 0.15, layer: "top" },
{ route_type: "via", x: 2.4, y: 3.0, from_layer: "top", to_layer: "inner2", via_diameter: 0.45, via_hole_diameter: 0.3 },
{ route_type: "wire", x: 2.4, y: 3.0, width: 0.15, layer: "inner2" },
{ route_type: "wire", x: 1.9, y: 4.2, width: 0.15, layer: "inner2" },
{ route_type: "wire", x: 1.9, y: 8.0, width: 0.15, layer: "inner2" },
{ route_type: "wire", x: -0.69, y: 8.0, width: 0.15, layer: "inner2" },
{ route_type: "via", x: -0.69, y: 8.0, from_layer: "inner2", to_layer: "bottom", via_diameter: 0.45, via_hole_diameter: 0.3 },
{ route_type: "wire", x: -0.69, y: 8.0, width: 0.15, layer: "bottom" },
{ route_type: "wire", x: -0.69, y: 8.6, width: 0.15, layer: "bottom" },
])
}
if (traceIdentity.includes("DATA_CC2_TO_RD") || touches(1.31, 8.6)) {
return replaceAutoroutedRoute(trace, [
{ route_type: "wire", x: -0.75, y: 3.876, width: 0.15, layer: "top" },
{ route_type: "wire", x: -0.75, y: 3.1, width: 0.15, layer: "top" },
{ route_type: "via", x: -0.75, y: 3.1, from_layer: "top", to_layer: "inner2", via_diameter: 0.45, via_hole_diameter: 0.3 },
{ route_type: "wire", x: -0.75, y: 3.1, width: 0.15, layer: "inner2" },
{ route_type: "wire", x: -0.75, y: 7.4, width: 0.15, layer: "inner2" },
{ route_type: "wire", x: 1.31, y: 7.4, width: 0.15, layer: "inner2" },
{ route_type: "via", x: 1.31, y: 7.4, from_layer: "inner2", to_layer: "bottom", via_diameter: 0.45, via_hole_diameter: 0.3 },
{ route_type: "wire", x: 1.31, y: 7.4, width: 0.15, layer: "bottom" },
{ route_type: "wire", x: 1.31, y: 8.6, width: 0.15, layer: "bottom" },
])
}
if (traceIdentity.includes("USB_DM_ESD_TO_MCU") || traceIdentity.includes("source_trace_34") || touches(2.15, 6.1491)) {
return replaceAutoroutedRoute(trace, [
{ route_type: "wire", x: 2.15, y: 6.1491, width: 0.15, layer: "bottom" },
{ route_type: "wire", x: 3.6, y: 6.0, width: 0.15, layer: "bottom" },
{ route_type: "via", x: 3.6, y: 6.0, from_layer: "bottom", to_layer: "inner2", via_diameter: 0.45, via_hole_diameter: 0.3 },
{ route_type: "wire", x: 3.6, y: 6.0, width: 0.15, layer: "inner2" },
{ route_type: "wire", x: 6.8, y: 6.0, width: 0.15, layer: "inner2" },
{ route_type: "wire", x: 9.0, y: 3.8, width: 0.15, layer: "inner2" },
{ route_type: "wire", x: 9.0, y: -2.3, width: 0.15, layer: "inner2" },
{ route_type: "via", x: 9.0, y: -2.3, from_layer: "inner2", to_layer: "bottom", via_diameter: 0.45, via_hole_diameter: 0.3 },
{ route_type: "wire", x: 9.0, y: -2.3, width: 0.15, layer: "bottom" },
{ route_type: "wire", x: 6.2, y: -2.3, width: 0.15, layer: "bottom" },
{ route_type: "wire", x: 5.7, y: -2.0, width: 0.15, layer: "bottom" },
{ route_type: "wire", x: 5.7, y: -1.5, width: 0.15, layer: "bottom" },
])
}
if (traceIdentity.includes("USB_DP_TO_BOOT_SWITCH") || traceIdentity.includes("source_trace_36") || (touches(5.3, -1.5) && touches(7.6, 6.150492))) {
return replaceAutoroutedRoute(trace, [
{ route_type: "wire", x: 5.3, y: -1.5, width: 0.15, layer: "bottom" },
{ route_type: "wire", x: 5.3, y: -1.9, width: 0.15, layer: "bottom" },
{ route_type: "via", x: 5.3, y: -1.9, from_layer: "bottom", to_layer: "inner1", via_diameter: 0.45, via_hole_diameter: 0.3 },
{ route_type: "wire", x: 5.3, y: -1.9, width: 0.15, layer: "inner1" },
{ route_type: "wire", x: 8.0, y: -1.9, width: 0.15, layer: "inner1" },
{ route_type: "wire", x: 8.0, y: 5.5, width: 0.15, layer: "inner1" },
{ route_type: "wire", x: 8.5, y: 5.5, width: 0.15, layer: "inner1" },
{ route_type: "via", x: 8.5, y: 5.5, from_layer: "inner1", to_layer: "top", via_diameter: 0.45, via_hole_diameter: 0.3 },
{ route_type: "wire", x: 8.5, y: 5.5, width: 0.15, layer: "top" },
{ route_type: "wire", x: 7.6, y: 6.150492, width: 0.15, layer: "top" },
])
}
return trace
})
// The default solver is deterministic for this dense 20 mm layout. Apply a
// small set of deterministic clearance corrections to its completed routes.
// The default autorouter still provides the topology and the untouched routes.
const applyDeterministicClearanceCorrections = (traces: any[]) => {
const correctionMode = (globalThis as any).process?.env?.TSCI_CORRECTION_MODE ?? "generic"
const fusePlacementShim = 0.2
const pointMoves = [
{ from: [0.6072492456800926, 4.83008417789855], to: [0.4072, 4.6301] },
{ from: [-2.859910649073286, 1.6044369571612076], to: [-2.7599, 1.7044] },
{ from: [-2.4924490000000006, -2.7750009999999996], to: [-2.3924, -2.575] },
] as const
const matches = (point: any, [x, y]: readonly [number, number]) =>
Math.hypot((point.x ?? Infinity) - x, (point.y ?? Infinity) - y) < 1e-5
const wire = (layer: string, x: number, y: number, width = 0.15) =>
({ route_type: "wire", layer, x, y, width })
const via = (fromLayer: string, toLayer: string, x: number, y: number) => ({
route_type: "via",
x,
y,
from_layer: fromLayer,
to_layer: toLayer,
via_diameter: 0.45,
via_hole_diameter: 0.3,
})
const enableToPullupTraceId = "source_trace_42__source_trace_43_mst0_0"
const enableToMcuTraceId = "source_trace_42__source_trace_43_mst1_0"
const logicInputTraceId = "source_trace_14__source_trace_15__source_trace_16_mst1_0"
const vioTraceId = "source_trace_17__source_trace_18__source_trace_19__source_trace_20__source_trace_21__source_trace_22__source_trace_23__source_trace_24__source_trace_25_mst8_0"
const vmSenseBTraceId = "source_trace_3__source_trace_4__source_trace_5__source_trace_6__source_trace_7__source_trace_8__source_trace_9__source_trace_10__source_trace_11_mst8_0"
const corrected = traces.map((trace: any) => {
const route = trace.route ?? []
const touches = (x: number, y: number) => route.some((point: any) =>
Math.hypot((point.x ?? Infinity) - x, (point.y ?? Infinity) - y) < 0.02)
const isVmEdgeBranch = touches(7.79, -1.3) && touches(4.2, 2.575)
const movedRoute = route.map((point: any) => {
const move = pointMoves.find(({ from }) => matches(point, from))
if (move) {
return { ...point, x: move.to[0], y: move.to[1] }
}
// The solver sees F1 at its previous location to preserve the verified
// topology. Move the two routed pad endpoints to the physical F1
// location after routing.
if (matches(point, [8.4, -5.645]) || matches(point, [8.4, -2.755])) {
return { ...point, x: point.x - fusePlacementShim }
}
if (isVmEdgeBranch && point.x > 9.65) {
return { ...point, x: 9.65 }
}
return point
})
const movedTrace = { ...trace, route: movedRoute }
if (trace.pcb_trace_id === "source_trace_2_0") {
return {
...movedTrace,
route: movedRoute.map((point: any) => point.route_type === "wire"
? { ...point, x: Math.min(point.x, 9.5), width: 0.5 }
: point),
}
}
if (correctionMode === "all" && trace.pcb_trace_id === enableToPullupTraceId) {
return replaceAutoroutedRoute(movedTrace, [
wire("top", -1, -3),
wire("top", -1, -3.3),
wire("top", -0.75, -3.55),
wire("top", -0.75, -4.15),
wire("top", -1.6, -4.7),
via("top", "inner2", -1.6, -4.7),
wire("inner2", -1.6, -4.7),
wire("inner2", -4.5, -4),
via("inner2", "top", -4.5, -4),
wire("top", -4.5, -4),
wire("top", -3.69, -3),
])
}
if (correctionMode === "all" && trace.pcb_trace_id === enableToMcuTraceId) {
const firstInner2 = movedRoute.findIndex((point: any) =>
point.route_type === "wire" && point.layer === "inner2")
const lastPort = [...movedRoute].reverse()
.find((point: any) => point.end_pcb_port_id)?.end_pcb_port_id
const enableTail = firstInner2 >= 0 ? movedRoute.slice(firstInner2 + 1) : movedRoute
const prefixEnd = enableTail.findIndex((point: any) =>
matches(point, [6.074089912366923, -6.557597890782669]))
const repairedRoute = prefixEnd < 0
? [wire("inner2", -1.6, -4.7), ...enableTail]
: [
wire("inner2", -1.6, -4.7),
...enableTail.slice(0, prefixEnd + 1),
wire("inner2", 5.9, -6.0),
wire("inner2", 5.9, -4.8),
wire("inner2", 6.2, -4.7),
wire("inner2", 6.3, -3.6),
wire("inner2", 6.9, -3.0),
wire("inner2", 6.9, -1.9),
wire("inner2", 7.11, -1.5),
via("inner2", "bottom", 7.11, -1.5),
wire("bottom", 7.11, -1.5),
wire("bottom", 7.11, -0.81),
wire("bottom", 7.1, -0.8),
]
return {
...movedTrace,
route: repairedRoute.map((point: any, index: number) => ({
...point,
...(index === repairedRoute.length - 1 && lastPort ? { end_pcb_port_id: lastPort } : {}),
})),
}
}
if (["all", "logicvm"].includes(correctionMode) && trace.pcb_trace_id === logicInputTraceId) {
return replaceAutoroutedRoute(movedTrace, [
wire("bottom", 9.2, 3.5, 0.2),
wire("bottom", 9.55, 3.15, 0.2),
wire("bottom", 9.55, -2.425, 0.2),
wire("bottom", 9.0, -2.975, 0.2),
])
}
if (["all", "logicvm"].includes(correctionMode) && trace.pcb_trace_id === vmSenseBTraceId) {
return {
...movedTrace,
route: movedRoute.flatMap((point: any) =>
point.route_type === "wire" && point.layer === "bottom" &&
matches(point, [-2.3924, -2.575])
? [{ ...point, x: -2.3, y: -3.1113 }, point]
: [point]),
}
}
return movedTrace
})
return corrected
}
const reconnectFrozenRoutesToCurrentPorts = (traces: any[], simpleRouteJson: any) => {
const routeRelocations = [
{ from: [6.461, -5.587], to: [6.261, -6.987] },
{ from: [8.015001, 1.4035478], to: [7.415, 2.0035] },
{ from: [-7.837, 2.186], to: [-7.837, 1.986] },
{ from: [5.442509, 6.102552], to: [5.2425, 6.1026] },
] as const
const currentPorts = new Map<string, { x: number; y: number; layer: string }>()
for (const connection of simpleRouteJson.connections ?? []) {
for (const point of connection.pointsToConnect ?? []) {
if (point.pcb_port_id) currentPorts.set(point.pcb_port_id, point)
}
}
const reconnected = traces.map((trace: any) => ({
...trace,
route: (trace.route ?? []).map((point: any) => {
const portId = point.start_pcb_port_id ?? point.end_pcb_port_id
const currentPort = portId ? currentPorts.get(portId) : undefined
const reconnected = currentPort
? { ...point, x: currentPort.x, y: currentPort.y,
...(point.route_type === "wire" ? { layer: currentPort.layer } : {}) }
: { ...point }
const relocation = routeRelocations.find(({ from }) =>
Math.hypot(reconnected.x - from[0], reconnected.y - from[1]) < 1e-4)
return relocation ? { ...reconnected, x: relocation.to[0], y: relocation.to[1] } : reconnected
}),
}))
// The released frozen route set predates the outer-layer load-current rule.
// Replace only the affected driver supply tie and motor phase; the rest of
// the verified autorouter result remains untouched.
const routeWire = (layer: string, x: number, y: number, width: number) =>
({ route_type: "wire", layer, x, y, width })
const routeVia = (fromLayer: string, toLayer: string, x: number, y: number) => ({
route_type: "via", x, y, from_layer: fromLayer, to_layer: toLayer,
via_diameter: 0.45, via_hole_diameter: 0.3,
})
const criticalOuterLayerRoutes = new Map<string, any[]>([
["source_trace_3__source_trace_4__source_trace_5__source_trace_6__source_trace_7__source_trace_8__source_trace_9__source_trace_10__source_trace_11_mst2_0", [
routeWire("top", -2.5, -2, 0.28), routeWire("top", -2.5, -2.14, 0.28),
routeWire("top", -2.5, -2.36, 0.5), routeWire("top", -2.5, -2.73, 0.56),
routeWire("top", -2.975, -3.05, 0.56), routeVia("top", "bottom", -2.975, -3.05),
routeWire("bottom", -2.975, -3.05, 0.56), routeWire("bottom", -2.0, -3.05, 0.56),
routeWire("bottom", -2.0, 1.82, 0.56), routeWire("bottom", -2.4, 1.82, 0.325),
routeWire("bottom", -2.7599, 1.7044, 0.325), routeVia("bottom", "top", -2.7599, 1.7044),
routeWire("top", -2.7599, 1.7044, 0.3),
routeWire("top", -2.859910649073286, 1.359910649073286, 0.5),
routeWire("top", -2.64, 1.14, 0.5), routeWire("top", -2.5, 1, 0.28),
]],
["source_trace_57_0", [
routeWire("top", -1.5, 2, 0.28), routeWire("top", -1.8, 2.3, 0.45),
routeWire("top", -3.6, 2.4, 0.45), routeWire("top", -3.6, 1.7, 0.45),
routeWire("top", -8.2, 1.7, 0.45), routeWire("top", -8.531897157415033, 1.5, 0.45),
routeWire("top", -8.9250037, 1.499997, 0.45),
]],
["source_trace_44__source_trace_45_mst0_0", [
routeWire("top", -1.0, 2.0, 0.15), routeWire("top", -2.1, 4.9, 0.15),
routeVia("top", "inner2", -2.1, 4.9), routeWire("inner2", -2.1, 4.9, 0.15),
routeWire("inner2", -3.0, 4.3, 0.15), routeWire("inner2", -3.4, 4.3, 0.15),
routeWire("inner2", -3.8, 4.8, 0.15), routeWire("inner2", -7.3, 4.9, 0.15),
routeWire("inner2", -7.4, 4.8, 0.15), routeVia("inner2", "top", -7.4, 4.8),
routeWire("top", -7.4, 4.8, 0.15), routeWire("top", -7.49, 4.8, 0.15),
]],
])
const outerLayerReconnected = reconnected.map((trace: any) => {
const route = criticalOuterLayerRoutes.get(trace.pcb_trace_id)
return route ? replaceAutoroutedRoute(trace, route) : trace
})
// The new lower-right motor mount consumes the old VM branch corridor. Keep
// this 0.56 mm branch on the outer layers and pass below the USB shell before
// returning to the PD logic diode; the only transition is a full-stack via.
const vmToLogicTraceId = "source_trace_3__source_trace_4__source_trace_5__source_trace_6__source_trace_7__source_trace_8__source_trace_9__source_trace_10__source_trace_11_mst1_0"
const vmSenseTraceId = "source_trace_3__source_trace_4__source_trace_5__source_trace_6__source_trace_7__source_trace_8__source_trace_9__source_trace_10__source_trace_11_mst5_0"
const vmBulkTieTraceId = "source_trace_3__source_trace_4__source_trace_5__source_trace_6__source_trace_7__source_trace_8__source_trace_9__source_trace_10__source_trace_11_mst3_0"
const vmBulkToDriverTraceId = "source_trace_3__source_trace_4__source_trace_5__source_trace_6__source_trace_7__source_trace_8__source_trace_9__source_trace_10__source_trace_11_mst8_0"
const logicInputTraceId = "source_trace_14__source_trace_15__source_trace_16_mst1_0"
const vbusAdcTraceId = "source_trace_38__source_trace_39_mst1_0"
const stepTraceId = "source_trace_40_0"
const vrefDriverTraceId = "source_trace_50__source_trace_51_mst0_0"
const bootSignalTraceId = "source_trace_35__source_trace_36_mst0_0"
return outerLayerReconnected.map((trace: any) => {
// Open a low-current breakout channel for PA2. Both transitions are
// ordinary full-stack through-vias; the signal uses inner2 only between
// those through-vias.
if (trace.pcb_trace_id === "source_trace_41_0") return replaceAutoroutedRoute(trace, [
{ route_type: "wire", x: -0.5, y: 2.0, width: 0.15, layer: "top" },
{ route_type: "wire", x: -0.3016298817149865, y: 2.5625, width: 0.15, layer: "top" },
{ route_type: "wire", x: -0.15162988171498704, y: 2.7875, width: 0.15, layer: "top" },
{ route_type: "via", x: -0.15162988171498704, y: 2.7875,
from_layer: "top", to_layer: "bottom", via_diameter: 0.45, via_hole_diameter: 0.3 },
{ route_type: "wire", x: -0.15162988171498704, y: 2.7875, width: 0.15, layer: "inner2" },
{ route_type: "wire", x: 0.0733701182850135, y: 2.4125, width: 0.15, layer: "inner2" },
{ route_type: "wire", x: 2.2483701182850133, y: 0.9125, width: 0.15, layer: "inner2" },
{ route_type: "wire", x: 3.348, y: 0.012, width: 0.15, layer: "inner2" },
{ route_type: "via", x: 3.348, y: 0.012,
from_layer: "top", to_layer: "bottom", via_diameter: 0.45, via_hole_diameter: 0.3 },
{ route_type: "wire", x: 3.348, y: 0.012, width: 0.15, layer: "bottom" },
{ route_type: "wire", x: 3.6, y: 0.1, width: 0.15, layer: "bottom" },
{ route_type: "wire", x: 4.1, y: 0.0, width: 0.15, layer: "bottom" },
])
if (trace.pcb_trace_id === vmToLogicTraceId) return replaceAutoroutedRoute(trace, [
{ route_type: "wire", x: 3.21, y: -4.3, width: 0.56, layer: "top" },
{ route_type: "wire", x: 3.5, y: -4.3, width: 0.56, layer: "top" },
{ route_type: "wire", x: 3.5, y: -4.6, width: 0.56, layer: "top" },
{ route_type: "via", x: 3.5, y: -4.6, from_layer: "bottom", to_layer: "top",
via_diameter: 0.45, via_hole_diameter: 0.3 },
{ route_type: "wire", x: 3.5, y: -4.6, width: 0.56, layer: "bottom" },
{ route_type: "wire", x: 2.8, y: -4.8, width: 0.56, layer: "bottom" },
{ route_type: "wire", x: 2.8, y: -7.15, width: 0.56, layer: "bottom" },
{ route_type: "wire", x: 5.0, y: -7.15, width: 0.56, layer: "bottom" },
{ route_type: "wire", x: 5.5888, y: -5.2050038, width: 0.56, layer: "bottom" },
])
if (trace.pcb_trace_id === vmSenseTraceId) return replaceAutoroutedRoute(trace, [
{ route_type: "wire", x: 5.5888, y: -5.2050038, width: 0.56, layer: "bottom" },
{ route_type: "wire", x: 6.0, y: -5.9, width: 0.56, layer: "bottom" },
{ route_type: "wire", x: 6.3, y: -5.9, width: 0.56, layer: "bottom" },
{ route_type: "wire", x: 5.925, y: -7.575, width: 0.56, layer: "bottom" },
{ route_type: "via", x: 5.925, y: -7.575, from_layer: "bottom", to_layer: "inner1",
via_diameter: 0.45, via_hole_diameter: 0.3 },
...trace.route.slice(7),
])
if (trace.pcb_trace_id === vmBulkTieTraceId) return replaceAutoroutedRoute(trace, [
routeWire("bottom", -8.4, -1.4575, 0.56),
routeWire("bottom", -7.45, -1.4575, 0.56),
routeWire("bottom", -7.45, 0.3675, 0.56),
routeWire("bottom", -8.9, 0.3675, 0.56),
])
if (trace.pcb_trace_id === vmBulkToDriverTraceId) return replaceAutoroutedRoute(trace, [
routeWire("bottom", -8.9, 0.3675, 0.56),
routeWire("bottom", -7.45, 0.3675, 0.56),
routeWire("bottom", -7.45, -3.35, 0.56),
routeWire("bottom", -3.67, -3.35, 0.56),
routeWire("bottom", -3.43, -3.11, 0.5),
routeWire("bottom", -2.91, -3.11, 0.475),
routeWire("bottom", -2.89, -3.1113, 0.28),
routeWire("bottom", -2.3, -3.1113, 0.28),
routeWire("bottom", -2.3924, -2.575, 0.28),
routeVia("bottom", "top", -2.3924, -2.575),
routeWire("top", -2.3924, -2.575, 0.56),
routeWire("top", -2.492449, -2.223694, 0.56),
routeWire("top", -2.384377, -2.115623, 0.5),
routeWire("top", -2.5, -2.0, 0.28),
])
if (trace.pcb_trace_id === logicInputTraceId) return replaceAutoroutedRoute(trace, [
routeWire("bottom", 8.2, 4.599998, 0.25),
routeWire("bottom", 8.35, 4.15, 0.25),
routeVia("bottom", "inner2", 8.35, 4.15),
routeWire("inner2", 8.35, 4.15, 0.25),
routeWire("inner2", 8.35, 2.0, 0.25),
routeWire("inner2", 9.25, 2.0, 0.25),
routeWire("inner2", 9.25, 0.85, 0.25),
routeWire("inner2", 9.25, 0.55, 0.25),
routeWire("inner2", 9.55, 0.25, 0.25),
routeWire("inner2", 9.55, -1.1, 0.25),
routeVia("inner2", "bottom", 9.55, -1.1),
routeWire("bottom", 9.55, -1.1, 0.25),
routeWire("bottom", 9.25, -1.25, 0.25),
routeWire("bottom", 8.95, -1.55, 0.25),
routeWire("bottom", 8.95, -2.15, 0.25),
routeWire("bottom", 8.65, -2.6, 0.25),
routeWire("bottom", 8.65, -2.9, 0.25),
routeWire("bottom", 8.5, -3.075, 0.25),
])
if (trace.pcb_trace_id === vbusAdcTraceId) return replaceAutoroutedRoute(trace, [
routeWire("top", 7.79, 0, 0.15),
routeWire("top", 8.125, 0.9, 0.15),
routeVia("top", "bottom", 8.125, 0.9),
routeWire("bottom", 8.125, 0.9, 0.15),
routeWire("bottom", 8.098370118285013, 0.9875, 0.15),
routeWire("bottom", 7.873370118285013, 0.9875, 0.15),
routeWire("bottom", 6.523370118285014, 2.1125, 0.15),
routeWire("bottom", 6.223370118285013, 2.1125, 0.15),
routeWire("bottom", 6.073370118285013, 1.8875, 0.15),
routeWire("bottom", 6, 1.5, 0.15),
])
if (trace.pcb_trace_id === stepTraceId) return replaceAutoroutedRoute(trace, [
...trace.route.slice(0, 8),
routeWire("inner2", 7.3, 0.2, 0.15),
routeWire("inner2", 8.773370118285012, 0.6875, 0.15),
...trace.route.slice(9),
])
// Keep the low-current VREF branch clear of the local VIO bypass placed
// directly under the driver's VCC_IO pin. The endpoints and layer
// transition are unchanged; only the bottom-layer dogleg is moved.
if (trace.pcb_trace_id === vrefDriverTraceId) return replaceAutoroutedRoute(trace, [
routeWire("bottom", 1.8, 0.51, 0.15),
routeWire("bottom", 0.9, -0.19, 0.15),
routeWire("bottom", 0.7, -0.29, 0.15),
routeWire("bottom", 0.4, -0.09, 0.15),
routeWire("bottom", 0.3, 0.01, 0.15),
routeWire("bottom", 0.2, 2.31, 0.15),
routeWire("bottom", 0.4483701182850135, 2.7875, 0.15),
routeVia("bottom", "top", 0.4483701182850135, 2.7875),
routeWire("top", 0.4483701182850135, 2.7875, 0.15),
routeWire("top", 0.5, 2.0, 0.15),
])
// U_3V3 moved away from the upper-right M2 screw envelope. Keep the BOOT
// transition outside the regulator pads by running on inner2 to the open
// right-edge corridor before returning to the top layer.
if (trace.pcb_trace_id === bootSignalTraceId) return replaceAutoroutedRoute(trace, [
routeWire("bottom", 5.6, -1.5, 0.15),
routeWire("bottom", 5.698370118285013, -2.2375, 0.15),
routeVia("bottom", "inner1", 5.698370118285013, -2.2375),
routeWire("inner1", 5.698370118285013, -2.2375, 0.15),
routeWire("inner1", 6.298370118285012, 0.8375, 0.15),
routeWire("inner1", 6.6, 2.7, 0.15),
routeWire("inner1", 6.8, 3.4, 0.15),
routeVia("inner1", "inner2", 6.8, 3.4),
routeWire("inner2", 6.8, 3.4, 0.15),
routeWire("inner2", 6.8, 4.7, 0.15),
{ route_type: "wire", x: 8.9, y: 4.7, width: 0.15, layer: "inner2" },
{ route_type: "via", x: 8.9, y: 4.7, from_layer: "inner2", to_layer: "top",
via_diameter: 0.45, via_hole_diameter: 0.3 },
{ route_type: "wire", x: 8.9, y: 4.7, width: 0.15, layer: "top" },
trace.route.at(-1),
])
return trace
})
}
// These low-current accessory routes are intentionally explicit because the
// 20 mm board has no spare outer-layer corridor through the driver/MCU core.
// They are emitted through the board autorouter (rather than trace pcbPath)
// so allowBlindAndBuriedVias=false expands every transition into a physical
// top-to-bottom plated through-via while retaining the selected signal layer.
const appendManualAccessoryRoutes = (traces: any[], simpleRouteJson: any) => {
const wire = (layer: string, x: number, y: number) =>
({ route_type: "wire", layer, x, y, width: 0.15 })
const via = (fromLayer: string, toLayer: string, x: number, y: number) => ({
route_type: "via",
x,
y,
from_layer: fromLayer,
to_layer: toLayer,
via_diameter: 0.45,
via_hole_diameter: 0.3,
})
const specifications = [
{
endpoints: [[5.2, 1.5], [5.42, 1]],
route: [
wire("bottom", 5.2, 1.5), wire("bottom", 5.1, 2.2),
via("bottom", "top", 5.1, 2.2), wire("top", 5.1, 2.2),
wire("top", 4.3, 1.4), via("top", "inner2", 4.3, 1.4),
wire("inner2", 4.3, 1.4), wire("inner2", 5.7, 0.5),
wire("inner2", 7.5, -1.3), wire("inner2", 7.6, -1.5),
wire("inner2", 7.4, -2.5), via("inner2", "top", 7.4, -2.5),
wire("top", 7.4, -2.5), wire("top", 6.5, -1.4),
wire("top", 6.2, -0.2), wire("top", 5.9, 0.3), wire("top", 5.42, 1),
],
},
{
endpoints: [[5.6, 1.5], [4.25, -1.5]],
route: [
wire("bottom", 5.6, 1.5), wire("bottom", 5.7, 2.3),
via("bottom", "inner1", 5.7, 2.3), wire("inner1", 5.7, 2.3),
wire("inner1", 4.5, 0.7), wire("inner1", 4.2, -2.2),
via("inner1", "top", 4.2, -2.2), wire("top", 4.2, -2.2),
wire("top", 4.25, -1.5),
],
},
{
endpoints: [[3.5, 2.67], [5.6, 1.5]],
route: [
wire("bottom", 3.5, 2.67), wire("bottom", 3.3, 2.77),
via("bottom", "inner2", 3.3, 2.77), wire("inner2", 3.3, 2.77),
wire("inner2", 5.2, 2.77), wire("inner2", 5.7, 2.3),
via("inner2", "bottom", 5.7, 2.3), wire("bottom", 5.7, 2.3),
wire("bottom", 5.6, 1.5),
],
},
{
endpoints: [[3.5, 3.33], [5.91, 3]],
route: [
wire("bottom", 3.5, 3.33), wire("bottom", 3.9, 3.03),
wire("bottom", 3.9, 2.33), wire("bottom", 3.2, 1.73), wire("bottom", 2.6, 1.83),
via("bottom", "inner2", 2.6, 1.83), wire("inner2", 2.6, 1.83),
wire("inner2", 2.6, 2.33), wire("inner2", 3, 3.13),
wire("inner2", 5.8, 4.63), via("inner2", "bottom", 5.8, 4.63),
wire("bottom", 5.8, 4.63), wire("bottom", 5.91, 3),
],
},
{
endpoints: [[4.1, 0.4], [-6.48005, 4.15995]],
route: [
wire("bottom", 4.1, 0.4), wire("bottom", 3.7, 0.4), wire("bottom", 3.5, 0.6),
wire("bottom", 3.3, 0.6),
via("bottom", "inner2", 3.3, 0.6), wire("inner2", 3.3, 0.6),
wire("inner2", 3.9, 0.2), wire("inner2", 3.7, -0.4),
wire("inner2", 2.1, -0.4), wire("inner2", 0.9, 0.6),
wire("inner2", -4.7, 3.0),
via("inner2", "top", -4.7, 3.0), wire("top", -4.7, 3.0),
wire("top", -5.3, 3.6), wire("top", -6.3, 3.6),
wire("top", -6.3, 4.3),
wire("top", -6.48005, 4.15995),
],
},
{
endpoints: [[-5.67995, 4.15995], [-4.99, -4.7]],
route: [
wire("top", -5.67995, 4.15995), wire("top", -5.35, 4.4),
via("top", "inner2", -5.35, 4.4), wire("inner2", -5.35, 4.4),
wire("inner2", -6.15, 3.4), wire("inner2", -6.35, -2.2),
wire("inner2", -8.35, -4.2), wire("inner2", -8.95, -5.4),
via("inner2", "bottom", -8.95, -5.4), wire("bottom", -8.95, -5.4),
wire("bottom", -5.55, -5.2), wire("bottom", -4.99, -4.7),
],
},
] as const
const closeTo = (point: any, [x, y]: readonly number[]) =>
Math.hypot((point.x ?? Infinity) - x, (point.y ?? Infinity) - y) < 0.02
const additions = specifications.map((specification) => {
const connection = (simpleRouteJson.connections ?? []).find((candidate: any) =>
specification.endpoints.every((endpoint) =>
(candidate.pointsToConnect ?? []).some((point: any) => closeTo(point, endpoint))))
if (!connection) {
throw new Error(`Missing manual accessory connection ${JSON.stringify(specification.endpoints)}`)
}
const firstPort = (connection.pointsToConnect ?? []).find((point: any) =>
closeTo(point, specification.endpoints[0]))?.pcb_port_id
const lastPort = (connection.pointsToConnect ?? []).find((point: any) =>
closeTo(point, specification.endpoints[1]))?.pcb_port_id
return {
type: "pcb_trace",
pcb_trace_id: `${connection.name}_manual_accessory`,
connection_name: connection.name,
route: specification.route.map((point: any, index: number) => ({
...point,
...(index === 0 && firstPort ? { start_pcb_port_id: firstPort } : {}),
...(index === specification.route.length - 1 && lastPort ? { end_pcb_port_id: lastPort } : {}),
})),
}
})
return [...traces, ...additions]
}
// Keep inner1 dedicated to the ground plane and let low-current signals use
// inner2. Power, sense, and motor buses remain restricted to the outer layers.
// With allowBlindAndBuriedVias=false, core expands every routed transition to
// a plated hole spanning top, inner1, inner2, and bottom.
const outerLayerDefaultAutorouter = async (simpleRouteJson: any) => {
const fusePlacementShim = 0.2
const isFusePadObstacle = (obstacle: any) =>
obstacle.center.x > 7 && obstacle.center.y < -2 && (
obstacle.connectedTo?.includes("source_trace_2") ||
(obstacle.connectedTo?.includes("source_trace_0") &&
obstacle.connectedTo?.includes("source_trace_1"))
)
const guardedInput = {
...simpleRouteJson,
layerCount: 4,
allowBlindAndBuriedVias: false,
// Keep the already-verified default-router topology while F1 is moved
// 0.2 mm inward for a full-width 0.50 mm post-fuse edge escape.
obstacles: simpleRouteJson.obstacles.map((obstacle: any) => isFusePadObstacle(obstacle)
? { ...obstacle, center: { ...obstacle.center, x: obstacle.center.x + fusePlacementShim } }
: obstacle),
connections: simpleRouteJson.connections.map((connection: any) =>
["source_trace_0", "source_trace_1", "source_trace_2"].includes(connection.name)
? {
...connection,
pointsToConnect: connection.pointsToConnect.map((point: any) => point.x > 7
? { ...point, x: point.x + fusePlacementShim }
: point),
}
: connection),
}
const baselineTraces = (releaseV1011AutorouterTraces as any[]).map((trace) => ({
...trace,
route: trace.route.map((point: any) => ({ ...point })),
}))
let correctedTraces: any[] | undefined
const listeners: Record<string, Array<(event: any) => void>> = {
complete: [], error: [], progress: [],
}
return {
on(eventName: string, callback: (event: any) => void) {
listeners[eventName]?.push(callback)
},
start() {
setTimeout(() => {
try {
const routeMode = (globalThis as any).process?.env?.TSCI_ROUTE_MODE ?? "baseline"
let traces = reconnectFrozenRoutesToCurrentPorts(baselineTraces, guardedInput)
if (routeMode === "incremental") {
const currentPorts = new Map<string, { x: number; y: number; layer: string }>()
for (const connection of guardedInput.connections ?? []) {
for (const point of connection.pointsToConnect ?? []) {
if (point.pcb_port_id) currentPorts.set(point.pcb_port_id, point)
}
}
const affectedSourceTraceNames = new Set<string>()
for (const trace of baselineTraces) {
const endpointMoved = trace.route.some((point: any) => {
const portId = point.start_pcb_port_id ?? point.end_pcb_port_id
const currentPort = portId ? currentPorts.get(portId) : undefined
return currentPort && Math.hypot(point.x - currentPort.x, point.y - currentPort.y) > 1e-4
})
if (!endpointMoved) continue
for (const name of trace.pcb_trace_id.match(/source_trace_\d+/g) ?? []) {
affectedSourceTraceNames.add(name)
}
}
const forcedFrozenNames = new Set([
"source_trace_0", "source_trace_1", "source_trace_2",
"source_trace_3", "source_trace_4", "source_trace_5", "source_trace_6",
"source_trace_7", "source_trace_8", "source_trace_9", "source_trace_10",
"source_trace_11",
"source_trace_12", "source_trace_13", "source_trace_14", "source_trace_15",
"source_trace_16", "source_trace_17", "source_trace_18", "source_trace_19",
"source_trace_20", "source_trace_21", "source_trace_22", "source_trace_23",
"source_trace_24", "source_trace_25",
"source_trace_35", "source_trace_36", "source_trace_37", "source_trace_38",
"source_trace_39",
])
const isAffected = (trace: any) => {
const names = trace.pcb_trace_id.match(/source_trace_\d+/g) ?? []
return !names.some((name: string) => forcedFrozenNames.has(name)) &&
names.some((name: string) => affectedSourceTraceNames.has(name))
}
const reconnectedBaseline = reconnectFrozenRoutesToCurrentPorts(baselineTraces, guardedInput)
const frozenTraces = reconnectedBaseline.filter((trace) => !isAffected(trace))
const incrementalSolver = new AutoroutingPipelineSolver9_PreloadedTraceGraph({
...guardedInput,
traces: frozenTraces,
connections: guardedInput.connections.filter((connection: any) =>
affectedSourceTraceNames.has(connection.name) &&
!forcedFrozenNames.has(connection.name)),
}, { effort: 2 })
incrementalSolver.solve()
if (incrementalSolver.failed) {
throw new Error(incrementalSolver.error ?? "Incremental reroute failed")
}
traces = [...frozenTraces, ...incrementalSolver.getOutputSimplifiedPcbTraces()]
} else if (routeMode === "hybrid") {
// The normal hosted build reuses the reviewed frozen default-router
// result below. Constructing the capacity solver is expensive even
// when it is never solved, so only create it for the explicit
// diagnostic hybrid mode.
const solver = new AutoroutingPipelineSolver9_PreloadedTraceGraph(guardedInput, { effort: 2 })
solver.solve()
if (solver.failed) throw new Error(solver.error ?? "Targeted reroute failed")
const routedTraces = solver.getOutputSimplifiedPcbTraces()
const currentPorts = new Map<string, { x: number; y: number; layer: string }>()
for (const connection of guardedInput.connections ?? []) {
for (const point of connection.pointsToConnect ?? []) {
if (point.pcb_port_id) currentPorts.set(point.pcb_port_id, point)
}
}
const affectedSourceTraceNames = new Set<string>()
for (const trace of baselineTraces) {
const endpointMoved = trace.route.some((point: any) => {
const portId = point.start_pcb_port_id ?? point.end_pcb_port_id
const currentPort = portId ? currentPorts.get(portId) : undefined
return currentPort && Math.hypot(point.x - currentPort.x, point.y - currentPort.y) > 1e-4
})
if (!endpointMoved) continue
for (const name of trace.pcb_trace_id.match(/source_trace_\d+/g) ?? []) {
affectedSourceTraceNames.add(name)
}
}
const isAffected = (trace: any) =>
(trace.pcb_trace_id.match(/source_trace_\d+/g) ?? [])
.some((name: string) => affectedSourceTraceNames.has(name))
traces = [
...baselineTraces.filter((trace) => !isAffected(trace)),
...routedTraces.filter(isAffected),
]
}
traces = appendManualAccessoryRoutes(traces, guardedInput)
correctedTraces = traces
listeners.complete.forEach((callback) => callback({ type: "complete", traces }))
} catch (cause) {
const error = cause instanceof Error ? cause : new Error(String(cause))
listeners.error.forEach((callback) => callback({ type: "error", error }))
}
}, 0)
},
stop() {
// The synchronous local solver has already completed when core calls stop.
},
getOutputSimpleRouteJson() {
return correctedTraces ? { ...guardedInput, traces: correctedTraces } : guardedInput
},
}
}
export default function Nema8FourLayerController() {
return (
<assembly.device name="NEMA8_CONTROLLER_ASSEMBLY">
<assembly.motor
name="MOTOR_8HS15_0604S"
displayName="StepperOnline 8HS15-0604S"
model={motorModel}
shaftFacingDirection="z-"
/>
<assembly.cable
name="MOTOR_HARNESS"
from="MOTOR_8HS15_0604S.wireside"
to=".CONTROLLER_PCB > .J_MOTOR_ASSEMBLY_ENDPOINT"
/>
<board
name="CONTROLLER_PCB"
mountedTo="MOTOR_8HS15_0604S.backface"
mountGap={motorToBoardMountGap}
width="20mm"
height="20mm"
layers={4}
thickness="1.6mm"
fabricatorPreset="jlcpcb_standard_20260912"
autorouterEffortLevel="2x"
minTraceWidth="0.15mm"
minTraceToPadEdgeClearance="0.1mm"
minTraceToHoleEdgeClearance="0.2mm"
minViaEdgeToPadEdgeClearance="0.1mm"
minViaHoleEdgeToViaHoleEdgeClearance="0.2mm"
minPlatedHoleDrillEdgeToDrillEdgeClearance="0.3mm"
minPadEdgeToPadEdgeClearance="0.1mm"
minBoardEdgeClearance="0.2mm"
minViaHoleDiameter="0.3mm"
minViaPadDiameter="0.45mm"
allowBlindAndBuriedVias={false}
isViaInPadAllowed
routeRemaining={false}
autorouterVersion="latest"
autorouter={{
preset: "default",
algorithmFn: outerLayerDefaultAutorouter,
allowViaInPad: false,
traceClearance: "0.1mm",
}}
pcbStyle={{ viaHoleDiameter: "0.3mm", viaPadDiameter: "0.45mm" }}
>
<schematicsheet name={sheets.power} displayName="1. USB-C PD and power" sheetSize="A4" sheetIndex={1}>
<schematicsection name={sections.pdInput} displayName="USB-C PD input and motor supply" />
<schematicsection name={sections.logicPower} displayName="3.3 V logic power" />
<schematictext schX={-13} schY={8.5} anchor="top_left" fontSize={0.22}
text="PWR / PD — vertical USB-C; CH32X035 negotiates motor voltage on the dedicated input." />
<schematictext schX={-13} schY={8} anchor="top_left" fontSize={0.19}
text="F1 protects the input; D_BLOCK limits reverse current; D_VM_TVS clamps VM transients." />
<schematictext schX={-13} schY={7.5} anchor="top_left" fontSize={0.19}
text="R_PD_CC1 and R_PD_CC2 provide independent 5.1 kΩ Rd pull-downs while CC1/CC2 remain connected to U_MCU." />
<schematictext schX={1} schY={8.5} anchor="top_left" fontSize={0.22}
text="LOGIC POWER — diode-ORed VM or DATA USB 5 V is regulated to 3.3 V." />
</schematicsheet>
<schematicsheet name={sheets.control} displayName="2. USB programming and controller" sheetSize="A4" sheetIndex={2}>
<schematicsection name={sections.usbData} displayName="USB-C data/programming" />
<schematicsection name={sections.controller} displayName="CH32X035 controller" />
<schematictext schX={-13} schY={8.5} anchor="top_left" fontSize={0.22}
text="DATA / PROG — vertical USB-C for USB 2.0 programming/data and optional 5 V logic power." />
<schematictext schX={-13} schY={8} anchor="top_left" fontSize={0.19}
text="Hold BOOT while connecting DATA / PROG to enter the ROM USB bootloader." />
<schematictext schX={1} schY={8.5} anchor="top_left" fontSize={0.22}
text="U_MCU negotiates PD and controls STEP, DIR, ENN, UART, and STDBY." />
</schematicsheet>
<schematicsheet name={sheets.driver} displayName="3. TMC2209 motor stage" sheetSize="A4" sheetIndex={3}>
<schematicsection name={sections.driverCore} displayName="TMC2209 driver and current regulation" />
<schematictext schX={-13} schY={8.5} anchor="top_left" fontSize={0.22}
text="U_DRV — top-side TMC2209 with a plated-through thermal-via field." />
<schematictext schX={-13} schY={8} anchor="top_left" fontSize={0.19}
text="UART changes run/hold current; the VREF network provides a hardware current ceiling." />
<schematictext schX={1} schY={8.5} anchor="top_left" fontSize={0.22}
text="MOTOR — 8HS15-0604S; JST pins 1-4: A+/BLK, A-/GRN, B+/RED, B-/BLU." />
</schematicsheet>
{nets.map((name) => (
<Fragment key={name}>
<net
name={name}
nominalTraceWidth={traceWidthForNet(name)}
isGroundNet={name === "GND"}
routingPhaseIndex={name === "GND" ? null : undefined}
/>
</Fragment>
))}
<copperpour name="GND_PLANE" layer="inner1" connectsTo="net.GND"
padMargin="0.3mm" traceMargin="0.3mm" boardEdgeMargin="0.25mm" useThermalReliefs />
{routedConnections.map(([from, to], index) => index === 40 || index === 48 || index >= 63 ? null : (
<Fragment key={`route-${index}`}>
<trace name={routeTraceNames[index]} from={from} to={to}
schDisplayLabel={routeSchematicLabels[index]}
thickness={traceWidthForRouteIndex(index)}
pcbPath={manualRouteIndexes.has(index) ? manualPcbPathForRouteIndex(index) : undefined}
routingPhaseIndex={routePhaseForIndex(index)} />
</Fragment>
))}
<bus name="PD_INPUT_BUS" connections={routeNames(0, 2)} routingPhaseIndex={1}
pcbTraceWidth="0.5mm" pcbAllowedLayers={["top", "bottom"]} preferredLayers={["top", "bottom"]} />
<bus name="VM_POWER_BUS" connections={routeNames(3, 11)} routingPhaseIndex={1}
pcbTraceWidth="0.56mm" pcbAllowedLayers={["top", "bottom"]} preferredLayers={["top", "bottom"]} />
<bus name="LOGIC_POWER_POLICY" connections={routeNames(12, 25)} routingPhaseIndex={1}
pcbAllowedLayers={["top", "inner2", "bottom"]} />
<bus name="PD_CC_SIGNAL_POLICY" connections={routeNames(26, 27)} routingPhaseIndex={1}
pcbAllowedLayers={["top", "inner2", "bottom"]} />
<bus name="PD_RD_SIGNAL_POLICY" connections={["PD_CC1_RD", "PD_CC2_RD"]} routingPhaseIndex={1}
pcbAllowedLayers={["top", "inner2", "bottom"]} />
<bus name="USB_SIGNAL_POLICY" connections={routeNames(28, 39)} routingPhaseIndex={1}
pcbAllowedLayers={["top", "inner2", "bottom"]} />
<bus name="STEP_SIGNAL_POLICY" connections={[routeTraceNames[41]]} routingPhaseIndex={1}
pcbAllowedLayers={["top", "inner2", "bottom"]} />
{routeNames(42, 47).map((routeName, offset) => (
<Fragment key={`control-signal-policy-${routeName}`}>
<bus name={`CONTROL_SIGNAL_POLICY_${offset + 1}`} connections={[routeName]}
routingPhaseIndex={1} pcbAllowedLayers={["top", "inner2", "bottom"]} />
</Fragment>
))}
{routeNames(49, 56).map((routeName, offset) => (
<Fragment key={`driver-local-policy-${routeName}`}>
<bus name={`DRIVER_LOCAL_POLICY_${offset + 1}`} connections={[routeName]}
routingPhaseIndex={1} pcbAllowedLayers={["top", "inner2", "bottom"]} />
</Fragment>
))}
<bus name="SENSE_BUS" connections={routeNames(57, 58)} routingPhaseIndex={1}
pcbTraceWidth="0.3mm" pcbAllowedLayers={["top", "bottom"]} preferredLayers={["top", "bottom"]} />
<bus name="MOTOR_A_POS_BUS" connections={[routeTraceNames[59]]} routingPhaseIndex={1}
pcbTraceWidth="0.45mm" pcbAllowedLayers={["top", "bottom"]} preferredLayers={["top", "bottom"]} />
<bus name="MOTOR_BUS" connections={routeNames(60, 62)} routingPhaseIndex={1}
pcbTraceWidth="0.3mm" pcbAllowedLayers={["top", "bottom"]} preferredLayers={["top", "bottom"]} />
<autoroutingphase name="DEFAULT_BOARD_ROUTING" phaseIndex={1}
algorithmFn={outerLayerDefaultAutorouter}
connections={[
...routeNames(0, 39),
"PD_CC1_RD",
"PD_CC2_RD",
...routeNames(41, 47),
...autoroutedRouteNames(49, 56),
...autoroutedRouteNames(57, 62),
"TEMP_SCL_MCU_FINAL",
"TEMP_SDA_MCU_FINAL",
"TEMP_SDA_PULLUP_FINAL",
"TEMP_SDA_PULLUP_VIO_FINAL",
"STATUS_LED_SIGNAL_FINAL",
"STATUS_LED_VIO_FINAL",
"STATUS_LED_GND_FINAL",
]} />
<USB4145_03_0070_C
name="J_USB_PD"
layer="top"
pcbX={0}
pcbY={-7.2}
pcbRotation={0}
schSectionName={sections.pdInput}
schSheetName={sheets.power}
schX={-11}
schY={3}
noConnect={["DP1", "DP2", "DN1", "DN2", "SBU1", "SBU2"]}
connections={{ GND1: "net.GND", GND2: "net.GND", GND3: "net.GND", GND4: "net.GND",
SHELL1: "net.GND", SHELL2: "net.GND", SHELL3: "net.GND", SHELL4: "net.GND" }}
/>
<USB4145_03_0070_C
name="J_USB_DATA"
layer="top"
pcbX={0}
pcbY={7.2}
pcbRotation={180}
schSectionName={sections.usbData}
schSheetName={sheets.control}
schX={-12.41}
schY={3}
noConnect={["SBU1", "SBU2"]}
connections={{ GND1: "net.GND", GND2: "net.GND", GND3: "net.GND", GND4: "net.GND",
SHELL1: "net.GND", SHELL2: "net.GND", SHELL3: "net.GND", SHELL4: "net.GND" }}
/>
{(["J_USB_PD", "J_USB_DATA"] as const).flatMap((connector) => ([
{ from: "VBUS1", to: "VBUS3", x: -1.0975, y: -1.48 },
{ from: "VBUS2", to: "VBUS4", x: 1.4025, y: -1.48 },
] as const).map(({ from, to, x, y }) => (
<Fragment key={`${connector}-${from}-${to}`}>
<trace name={`${connector}_${from}_TO_${to}`}
from={`.${connector} > .${from}`} to={`.${connector} > .${to}`}
thickness="0.3mm" pcbPathRelativeTo={`.${connector} > .${from}`}
pcbPath={[{ x, y }]} routingPhaseIndex={null} />
</Fragment>
)))}
<BM04B_SRSS_TB_LF__SN_
name="J_MOTOR"
layer="top"
pcbX={-7.6}
pcbY={0}
pcbRotation={270}
schSectionName={sections.driverCore}
schSheetName={sheets.driver}
schX={10}
schY={0}
noConnect={["pin5"]}
pcbPinLabels={{ pin1: "A+", pin2: "A-", pin3: "B+", pin4: "B-" }}
/>
<TMC2209_LA_T
name="U_DRV"
layer="top"
pcbX={driverX}
pcbY={driverY}
pcbRotation={0}
schSectionName={sections.driverCore}
schSheetName={sheets.driver}
schX={0}
schY={1}
schWidth={2.53}
schHeight={3.2}
noConnect={["INDEX", "DIAG"]}
/>
{thermalViaOffsets.map(([x, y]) => (
<Fragment key={`thermal-${x}-${y}`}>
<via
name={`U_DRV_THERMAL_${x}_${y}`}
pcbX={driverX + x}
pcbY={driverY + y}
fromLayer="top"
toLayer="bottom"
holeDiameter="0.3mm"
outerDiameter="0.45mm"
connectsTo="net.GND"
tented="bottom_tented"
/>
</Fragment>
))}
<CH32X035F8U6_ALT
name="U_MCU"
layer="bottom"
pcbX={mcuX}
pcbY={mcuY}
pcbRotation={180}
schSectionName={sections.controller}
schSheetName={sheets.control}
schX={4.5}
schY={2}
schWidth={1.865}
schHeight={2.4}
noConnect={["PA0", "PB0", "PB1", "PB3", "DIO", "DCK"]}
/>
<R name="R_PD_CC1" resistance="5.1k" layer="bottom" pcbX={-1.0} pcbY={-7.2} pcbRotation={0}
schSectionName={sections.pdInput} schSheetName={sheets.power} schX={-10} schY={-2} schRotation={-90}
connections={{ pin1: "net.PD_CC1", pin2: "net.GND" }} />
<R name="R_PD_CC2" resistance="5.1k" layer="bottom" pcbX={1.0} pcbY={-7.2} pcbRotation={180}
schSectionName={sections.pdInput} schSheetName={sheets.power} schX={-7} schY={-2} schRotation={-90}
connections={{ pin1: "net.PD_CC2", pin2: "net.GND" }} />
<trace name="PD_CC1_RD" from=".J_USB_PD > .CC1" to=".R_PD_CC1 > .pin1"
thickness="0.15mm" routingPhaseIndex={1} />
<trace name="PD_CC2_RD" from=".J_USB_PD > .CC2" to=".R_PD_CC2 > .pin1"
thickness="0.15mm" routingPhaseIndex={1} />
<R name="R_DATA_CC1" resistance="5.1k" layer="bottom" pcbX={-1.7} pcbY={7.2} pcbRotation={90}
schSectionName={sections.usbData} schSheetName={sheets.control} schX={-10} schY={-2} schRotation={-90}
connections={{ pin1: "net.DATA_CC1", pin2: "net.GND" }} />
<R name="R_DATA_CC2" resistance="5.1k" layer="bottom" pcbX={1.7} pcbY={7.2} pcbRotation={90}
schSectionName={sections.usbData} schSheetName={sheets.control} schX={-7.95} schY={-2} schRotation={-90}
connections={{ pin1: "net.DATA_CC2", pin2: "net.GND" }} />
<USBLC6_2SC6 name="U_USB_ESD" layer="bottom" pcbX={0} pcbY={7.2} pcbRotation={90}
schSectionName={sections.usbData} schSheetName={sheets.control} schX={-3.32} schY={3} />
<BAT54KFILM name="D_LOGIC_PD" layer="bottom" pcbX={6.3} pcbY={-5.2} pcbRotation={0}
schSectionName={sections.logicPower} schSheetName={sheets.power} schX={-4} schY={-3} schRotation={90} />
<BAT54WS name="D_LOGIC_USB" layer="bottom" pcbX={-6.6} pcbY={3.5} pcbRotation={90}
schSectionName={sections.logicPower} schSheetName={sheets.power} schX={0} schY={-3} schRotation={90} />
<HT7533_1 name="U_3V3" layer="bottom" pcbX={8.2} pcbY={3.6} pcbRotation={90}
schSectionName={sections.logicPower} schSheetName={sheets.power} schX={5} schY={-3}
schWidth={1.8} schHeight={1.0}
schPinArrangement={{
leftSide: { pins: [3], direction: "top-to-bottom" },
rightSide: { pins: [2], direction: "top-to-bottom" },
bottomSide: { pins: [1], direction: "left-to-right" },
}}
/>
<C name="C_LDO_IN" value="2.2uF" layer="bottom" pcbX={8.5} pcbY={-3.9} pcbRotation={90}
schSectionName={sections.logicPower} schSheetName={sheets.power} schX={3} schY={-5.5} schRotation={-90}
connections={{ pin1: "net.LOGIC_IN", pin2: "net.GND" }} />
<C name="C_3V3_BULK" value="2.2uF_10V" layer="bottom" pcbX={-5.5} pcbY={-4.7} pcbRotation={0}
schSectionName={sections.logicPower} schSheetName={sheets.power} schX={8} schY={-5.5} schRotation={-90}
connections={{ pin1: "net.VIO", pin2: "net.GND" }} />
<C name="C_MCU_HF" value="100nF" layer="bottom" pcbX={4.0} pcbY={-3.6} pcbRotation={180}
schSectionName={sections.controller} schSheetName={sheets.control} schX={10} schY={4.5} schRotation={-90}
connections={{ pin1: "net.VIO", pin2: "net.GND" }} />
<C name="C_MCU_BULK" value="2.2uF_10V" layer="bottom" pcbX={6.6} pcbY={-3.2} pcbRotation={180}
schSectionName={sections.controller} schSheetName={sheets.control} schX={10} schY={3} schRotation={-90}
connections={{ pin1: "net.VIO", pin2: "net.GND" }} />
<R name="R_VBUS_TOP" resistance="270k" layer="top" pcbX={8.3} pcbY={-1.3} pcbRotation={0}
schSectionName={sections.controller} schSheetName={sheets.control} schX={9} schY={-1}
connections={{ pin1: "net.VM", pin2: "net.VBUS_ADC" }} />
<R name="R_VBUS_BOTTOM" resistance="47k" layer="top" pcbX={8.3} pcbY={0} pcbRotation={0}
schSectionName={sections.controller} schSheetName={sheets.control} schX={11} schY={-1} schRotation={-90}
connections={{ pin1: "net.VBUS_ADC", pin2: "net.GND" }} />
<R name="R_BOOT" resistance="4.7k" layer="bottom" pcbX={5.4} pcbY={3.0} pcbRotation={0}
schSectionName={sections.controller} schSheetName={sheets.control} schX={7} schY={-4} schRotation={-90}
connections={{ pin1: "net.VIO", pin2: "net.BOOT_BIAS" }} />
<TL3780AF100QG name="SW_BOOT" layer="top" pcbX={9.03} pcbY={3.3} pcbRotation={90}
schSectionName={sections.controller} schSheetName={sheets.control} schX={11} schY={-4} />
<R name="R_EN_PU" resistance="100k" layer="top" pcbX={-4.2} pcbY={-3.0} pcbRotation={0}
schSectionName={sections.controller} schSheetName={sheets.control} schX={-1} schY={-4} schRotation={-90}
connections={{ pin1: "net.VIO", pin2: "net.ENN" }} />
<R name="R_STDBY_PD" resistance="100k" layer="top" pcbX={-8.0} pcbY={4.8} pcbRotation={180}
schSectionName={sections.controller} schSheetName={sheets.control} schX={1.5} schY={-4} schRotation={-90}
connections={{ pin1: "net.STDBY", pin2: "net.GND" }} />
<BSMD1206_110_16V name="F1" layer="top" pcbX={7.6} pcbY={-4.2} pcbRotation={0}
schSectionName={sections.pdInput} schSheetName={sheets.power} schX={-6} schY={4} />
<PMEG6020ELRX name="D_BLOCK" layer="bottom" pcbX={0} pcbY={-8.6} pcbRotation={0}
schSectionName={sections.pdInput} schSheetName={sheets.power} schX={-2} schY={4} />
<SMAJ16A name="D_VM_TVS" layer="bottom" pcbX={-0.3} pcbY={3.5} pcbRotation={180}
schSectionName={sections.pdInput} schSheetName={sheets.power} schX={1} schY={1} schRotation={-90}
connections={{ anode: "net.GND" }} />
{[
{ x: -8.4, y: -2.92, rotation: 90 },
{ x: -8.9, y: 1.83, rotation: 270 },
].map(({ x, y, rotation }, index) => (
<Fragment key={`bulk-${index}`}>
<C name={`C_VM_BULK${index + 1}`} value="47uF_25V"
layer="bottom" pcbX={x} pcbY={y} pcbRotation={rotation}
schSectionName={sections.pdInput} schSheetName={sheets.power}
schX={4 + index * 3} schY={1} schRotation={-90}
connections={{ pin1: "net.VM", pin2: "net.GND" }} />
</Fragment>
))}
<C name="C_VM_HF1" value="100nF_50V" layer="top" pcbX={4.2} pcbY={3.4} pcbRotation={90}
schSectionName={sections.driverCore} schSheetName={sheets.driver} schX={-10} schY={3} schRotation={-90}
connections={{ pin1: "net.VM", pin2: "net.GND" }} />
<C name="C_CP" value="22nF_50V" layer="top" pcbX={0.25} pcbY={-4.3} pcbRotation={0}
schSectionName={sections.driverCore} schSheetName={sheets.driver} schX={-6} schY={4}
connections={{ pin1: "net.CP_HI", pin2: "net.CP_LO" }} />
<capacitor name="C_VCP" capacitance="100nF" footprint="0402" maxVoltageRating="50V"
supplierPartNumbers={{ jlcpcb: ["C525226"] }} layer="top" pcbX={2.7} pcbY={-4.3} pcbRotation={0}
schSectionName={sections.driverCore} schSheetName={sheets.driver} schX={-6} schY={2}
schOrientation="vertical" schRotation={180} />
<C name="C_5V" value="2.2uF_10V" layer="top" pcbX={3.9} pcbY={-3.3} pcbRotation={0}
schSectionName={sections.driverCore} schSheetName={sheets.driver} schX={-6} schY={0} schRotation={-90}
connections={{ pin1: "net.V5_DRV", pin2: "net.GND" }} />
<C name="C_VIO" value="100nF" layer="top" pcbX={6.0} pcbY={3.5} pcbRotation={90}
schSectionName={sections.driverCore} schSheetName={sheets.driver} schX={-6} schY={-2} schRotation={-90}
connections={{ pin1: "net.VIO", pin2: "net.GND" }} />
<PT1206FR_7W0R33L name="R_SENSE_A" layer="bottom" pcbX={-4.5} pcbY={0.5} pcbRotation={0}
schSectionName={sections.driverCore} schSheetName={sheets.driver} schX={4} schY={-3} schRotation={-90} />
<PT1206FR_7W0R33L name="R_SENSE_B" layer="bottom" pcbX={-4.8} pcbY={-1.8} pcbRotation={0}
schSectionName={sections.driverCore} schSheetName={sheets.driver} schX={7} schY={-3} schRotation={-90} />
<R name="R_VREF_TOP" resistance="12k" layer="bottom" pcbX={1.8} pcbY={-2.3} pcbRotation={90}
schSectionName={sections.driverCore} schSheetName={sheets.driver} schX={4} schY={4}
connections={{ pin1: "net.V5_DRV", pin2: "net.VREF" }} />
<R name="R_VREF_BOTTOM" resistance="10k" layer="bottom" pcbX={1.8} pcbY={0} pcbRotation={90}
schSectionName={sections.driverCore} schSheetName={sheets.driver} schX={7} schY={4} schRotation={-90}
connections={{ pin1: "net.VREF", pin2: "net.GND" }} />
<C name="C_VREF" value="100nF" layer="bottom" pcbX={0.2} pcbY={-2.7} pcbRotation={0}
schSectionName={sections.driverCore} schSheetName={sheets.driver} schX={10} schY={4} schRotation={-90}
connections={{ pin1: "net.VREF", pin2: "net.GND" }} />
{groundFanouts.map(({ from, x, y, fromLayer }, index) => (
<Fragment key={`ground-fanout-${index}`}>
<trace name={`GROUND_FANOUT_${index + 1}`} from={from} to="net.GND"
thickness={from.includes("R_DATA_CC") ? "0.15mm" : "0.2mm"}
pcbPath={[{ x, y }, {
x, y, via: true, fromLayer,
toLayer: fromLayer === "top" ? "bottom" : "top",
}]}
routingPhaseIndex={null} />
</Fragment>
))}
<trace name="USB_ESD_GND_FANOUT" from=".U_USB_ESD > .GND" to="net.GND" thickness="0.2mm"
pcbPathRelativeTo=".U_USB_ESD > .GND"
pcbPath={[{ x: 0, y: 0, via: true, fromLayer: "bottom", toLayer: "top" }]}
routingPhaseIndex={null} />
<trace name="C_LDO_IN_GND_FANOUT" from=".C_LDO_IN > .pin2" to="net.GND" thickness="0.2mm"
pcbPath={[{ x: -0.1, y: 1.3 },
{ x: -0.1, y: 1.3, via: true, fromLayer: "bottom", toLayer: "top" }]}
routingPhaseIndex={null} />
<trace name="C_VREF_GND_FANOUT" from=".C_VREF > .pin2" to="net.GND" thickness="0.2mm"
pcbPath={[{ x: -1.4, y: -1.1 },
{ x: -1.4, y: -1.1, via: true, fromLayer: "bottom", toLayer: "top" }]}
routingPhaseIndex={null} />
<trace name="C_5V_GND_FANOUT" from=".C_5V > .pin2" to="net.GND" thickness="0.2mm"
pcbPath={[{ x: 0.7, y: -1.0 },
{ x: 0.7, y: -1.0, via: true, fromLayer: "top", toLayer: "bottom" }]}
routingPhaseIndex={null} />
<trace name="C_VIO_GND_FANOUT" from=".C_VIO > .pin2" to="net.GND" thickness="0.2mm"
pcbPathRelativeTo=".C_VIO > .pin2"
pcbPath={[
{ x: 0.51, y: -0.3 },
{ x: 0.51, y: -0.3, via: true, fromLayer: "top", toLayer: "bottom" },
]}
routingPhaseIndex={null} />
{(["J_USB_PD", "J_USB_DATA"] as const).flatMap((connector) =>
verticalUsbShellPaths.map(({ pin, x, y }) => {
const port = `.${connector} > .${pin}`
return (
<Fragment key={`${connector}-${pin}-shell`}>
<trace name={`${connector}_${pin}_SHELL_GROUND`}
from={port} to="net.GND" thickness="0.2mm"
pcbPathRelativeTo={port} pcbPath={[{ x, y }]}
routingPhaseIndex={null} />
</Fragment>
)
}),
)}
{driverEpGroundPaths.map(({ from, path }, index) => (
<Fragment key={`driver-ground-via-${index}`}>
<trace name={`U_DRV_GND_VIA_${index + 1}`} from={from} to="net.GND" thickness="0.15mm"
pcbPath={[...path]}
routingPhaseIndex={null} />
</Fragment>
))}
<trace name="U_DRV_EP_GND" from=".U_DRV > .EP" to="net.GND" thickness="0.15mm"
pcbPathRelativeTo=".U_DRV > .EP"
pcbPath={[{ x: 0, y: 0, via: true, fromLayer: "top", toLayer: "bottom" }]}
routingPhaseIndex={null} />
<trace name="U_MCU_EP_GND" from=".U_MCU > .GND" to="net.GND" thickness="0.15mm"
pcbPathRelativeTo=".U_MCU > .GND"
pcbPath={[{ x: 0, y: 0, via: true, fromLayer: "bottom", toLayer: "top" }]}
routingPhaseIndex={null} />
<TMP102AIDRLR
name="U_TEMP"
layer="top"
pcbX={5.0}
pcbY={-1.0}
pcbRotation={0}
schSectionName={sections.controller}
schSheetName={sheets.control}
schX={-4.37}
schY={-1.5}
noConnect={["ALERT"]}
/>
<R0201 name="R_TEMP_SCL" resistance="4.7k" layer="top"
pcbX={5.75} pcbY={1.0} pcbRotation={0}
schSectionName={sections.controller} schSheetName={sheets.control}
schX={-6.67} schY={-4.5} schRotation={-90} />
<R0201 name="R_TEMP_SDA" resistance="4.7k" layer="bottom"
pcbX={3.5} pcbY={3.0} pcbRotation={270}
schSectionName={sections.controller} schSheetName={sheets.control}
schX={-4} schY={-4.5} schRotation={-90} />
<C0201 name="C_TEMP" layer="top" pcbX={4.25} pcbY={0.5} pcbRotation={0}
schSectionName={sections.controller} schSheetName={sheets.control}
schX={10} schY={1.5} schRotation={-90} />
<WS2812B_1313_V6
name="D_STATUS"
layer="top"
pcbX={-6.08}
pcbY={4.56}
pcbRotation={180}
schSectionName={sections.controller}
schSheetName={sheets.control}
schX={-9.28}
schY={3}
noConnect={["DOUT"]}
/>
<C0201 name="C_STATUS" layer="bottom" pcbX={-4.3} pcbY={4.6} pcbRotation={180}
schSectionName={sections.controller} schSheetName={sheets.control}
schX={10} schY={0} schRotation={-90} />
{false && <>
<trace name="TEMP_SCL_MCU" from=".U_MCU > .I2C_SCL" to="net.TEMP_SCL"
thickness="0.15mm" pcbPathRelativeTo=".U_MCU > .I2C_SCL"
pcbPath={[
{ x: 0.6, y: -2.3 },
{ x: 0.6, y: -2.3, via: true, fromLayer: "bottom", toLayer: "top" },
{ x: 0.6, y: -2.3 },
{ x: -0.6, y: 0.0 },
]}
routingPhaseIndex={null} />
<trace name="TEMP_SCL_SENSOR" from=".U_TEMP > .SCL" to="net.TEMP_SCL"
thickness="0.15mm" pcbPathRelativeTo=".U_TEMP > .SCL"
pcbPath={[
{ x: 1.1, y: -0.4 },
{ x: 1.3, y: -0.2 },
{ x: 1.2, y: 1.0 },
]}
routingPhaseIndex={null} />
<trace name="TEMP_SDA_MCU" from=".U_MCU > .I2C_SDA" to="net.TEMP_SDA"
thickness="0.15mm" pcbPathRelativeTo=".U_MCU > .I2C_SDA"
pcbPath={[
{ x: 0.0, y: -2.1 },
{ x: 0.0, y: -2.1, via: true, fromLayer: "bottom", toLayer: "top" },
{ x: 0.0, y: -2.1 },
]}
routingPhaseIndex={null} />
<trace name="TEMP_SDA_SENSOR" from=".U_TEMP > .SDA" to="net.TEMP_SDA"
thickness="0.15mm" pcbPathRelativeTo=".U_TEMP > .SDA"
pcbPath={[
{ x: -0.8, y: -1.2 },
{ x: -0.8, y: -1.2, via: true, fromLayer: "top", toLayer: "inner2" },
{ x: -0.8, y: -1.2 },
{ x: -1.3, y: 1.3 },
{ x: -2.0, y: 2.0 },
{ x: -2.4, y: 3.3 },
{ x: -2.1, y: 3.6 },
{ x: -1.7, y: 3.6 },
{ x: -0.2, y: 3.7 },
{ x: 0.2, y: 3.7 },
{ x: 0.5, y: 3.4 },
{ x: 0.6, y: 3.1 },
]} routingPhaseIndex={null} />
<trace name="TEMP_SCL_PULLUP_TAP" from=".R_TEMP_SCL > .pin1" to="net.TEMP_SCL"
thickness="0.15mm" pcbPathRelativeTo=".R_TEMP_SCL > .pin1"
pcbPath={[
{ x: -0.33, y: 0.45 },
{ x: 0.5, y: 0.55 },
]} routingPhaseIndex={null} />
<trace name="TEMP_SDA_PULLUP_TAP" from=".R_TEMP_SDA > .pin1" to="net.TEMP_SDA"
thickness="0.15mm" pcbPathRelativeTo=".R_TEMP_SDA > .pin1"
pcbPath={[{ x: 1.1, y: 1.4 }]}
routingPhaseIndex={null} />
<trace name="TEMP_PULLUP_VIO_CHAIN" from=".R_TEMP_SCL > .pin2" to=".R_TEMP_SDA > .pin2"
thickness="0.15mm" pcbPathRelativeTo=".R_TEMP_SCL > .pin2"
pcbPath={[".R_TEMP_SDA > .pin2"]}
routingPhaseIndex={null} />
<trace name="TEMP_SDA_PULLUP_VIO" from=".R_TEMP_SDA > .pin2" to=".C_VIO > .pin1"
thickness="0.15mm" pcbPathRelativeTo=".R_TEMP_SDA > .pin2"
pcbPath={[
{ x: 0.6, y: -0.6 },
{ x: 0.9, y: -0.9 },
{ x: 2.0, y: -0.9 },
{ x: 2.3, y: -0.6 },
{ x: 2.1, y: 0.8 },
".C_VIO > .pin1",
]}
routingPhaseIndex={null} />
<trace name="TEMP_SENSOR_VIO" from=".C_TEMP > .pin1" to=".U_TEMP > .V_POS"
thickness="0.15mm" pcbPathRelativeTo=".C_TEMP > .pin1"
pcbPath={[
{ x: -0.73, y: -1.2 },
{ x: -0.73, y: -1.8 },
".U_TEMP > .V_POS",
]}
routingPhaseIndex={null} />
<trace name="TEMP_ACCESSORY_VIO_FEED" from=".C_TEMP > .pin1" to=".C_VIO > .pin1"
thickness="0.15mm" pcbPathRelativeTo=".C_TEMP > .pin1"
pcbPath={[".C_VIO > .pin1"]}
routingPhaseIndex={null} />
<trace name="TEMP_SENSOR_GND" from=".U_TEMP > .GND" to="net.GND"
thickness="0.15mm" pcbPathRelativeTo=".U_TEMP > .GND"
pcbPath={[
{ x: 0.35, y: 0.2 },
{ x: 0.25, y: 0.3 },
{ x: 0.25, y: 0.7 },
{ x: 0.55, y: 1.0 },
{ x: 0.6, y: 1.0 },
]}
routingPhaseIndex={null} />
<trace name="TEMP_ADD0_GND_FANOUT" from=".U_TEMP > .ADD0" to="net.GND"
thickness="0.15mm" pcbPathRelativeTo=".U_TEMP > .ADD0"
pcbPath={[{ x: 0.6, y: 1.0 }]}
routingPhaseIndex={null} />
<trace name="TEMP_CAP_GND_FANOUT" from=".C_TEMP > .pin2" to="net.GND"
thickness="0.15mm" pcbPathRelativeTo=".C_TEMP > .pin2"
pcbPath={[{ x: 1.1, y: -1.0 }]}
routingPhaseIndex={null} />
<trace name="STATUS_LED_DECOUPLING" from=".D_STATUS > .VDD" to=".C_STATUS > .pin1"
thickness="0.15mm" pcbPathRelativeTo=".D_STATUS > .VDD"
pcbPath={[".C_STATUS > .pin1"]} routingPhaseIndex={null} />
<trace name="STATUS_LED_VIO" from=".C_STATUS > .pin1" to=".U_MCU > .VDD"
thickness="0.15mm" pcbPathRelativeTo=".C_STATUS > .pin1"
pcbPath={[
{ x: 0.03, y: 0.4 },
{ x: -0.97, y: 0.5 },
{ x: -1.37, y: 0.5 },
{ x: -1.47, y: 0.4 },
{ x: -2.27, y: 0.4 },
{ x: -2.37, y: 0.5 },
{ x: -2.77, y: 0.5 },
{ x: -3.77, y: -0.5 },
{ x: -4.57, y: -0.5 },
{ x: -4.67, y: -0.6 },
{ x: -4.67, y: -1.4 },
{ x: -4.47, y: -1.9 },
{ x: -3.77, y: -2.6 },
".U_MCU > .VDD",
]}
routingPhaseIndex={null} />
<trace name="STATUS_LED_SIGNAL" from=".U_MCU > .STATUS_LED" to=".D_STATUS > .DIN"
thickness="0.15mm" pcbPathRelativeTo=".U_MCU > .STATUS_LED"
pcbPath={[
{ x: 2.3, y: -0.6 },
{ x: 2.3, y: -0.6, via: true, fromLayer: "bottom", toLayer: "inner2" },
{ x: 2.3, y: -0.6 },
{ x: 1.8, y: -0.2 },
{ x: 1.9, y: 0.3 },
{ x: 3.9, y: 2.0 },
{ x: 6.2, y: 5.2 },
{ x: 7.2, y: 5.3 },
{ x: 7.2, y: 5.3, via: true, fromLayer: "inner2", toLayer: "bottom" },
{ x: 7.2, y: 5.3 },
{ x: 7.6, y: 4.9 },
{ x: 7.6, y: 4.5 },
{ x: 7.4, y: 4.3 },
{ x: 5.2, y: 4.3 },
".D_STATUS > .DIN",
]}
routingPhaseIndex={null} />
<trace name="STATUS_LED_GND_LINK" from=".D_STATUS > .GND" to="net.GND"
thickness="0.15mm"
pcbPath={[
{ x: 3.1, y: 1.5 },
{ x: 3.1, y: 1.5, via: true, fromLayer: "bottom", toLayer: "top" },
{ x: 3.1, y: 1.5 },
]}
routingPhaseIndex={null} />
<trace name="STATUS_CAP_GND_FANOUT" from=".C_STATUS > .pin2" to="net.GND"
thickness="0.15mm" pcbPathRelativeTo=".C_STATUS > .pin2"
pcbPath={[{ x: -1.2, y: 0.1 }]}
routingPhaseIndex={null} />
</>}
{false && <>
<trace name="TEMP_SENSOR_VIO" from=".C_TEMP > .pin1" to=".U_TEMP > .V_POS"
thickness="0.15mm" pcbPathRelativeTo=".C_TEMP > .pin1" pcbPath={[
{ x: -0.75, y: -0.9 },
{ x: -0.75, y: -1.7 },
{ x: -0.65, y: -1.8 },
".U_TEMP > .V_POS",
]} routingPhaseIndex={null} />
<trace name="TEMP_ACCESSORY_VIO_FEED" from=".C_TEMP > .pin1" to=".C_VIO > .pin1"
thickness="0.15mm" pcbPathRelativeTo=".C_TEMP > .pin1" pcbPath={[
{ x: -0.33, y: 0.5 },
{ x: -0.33, y: 0.5, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: -0.33, y: 0.5 },
{ x: -1.23, y: 1.8 },
{ x: -1.23, y: 1.8, via: true, fromLayer: "bottom", toLayer: "inner2" },
{ x: -1.23, y: 1.8 },
{ x: 1.27, y: 3.7 },
{ x: 1.27, y: 3.7, via: true, fromLayer: "inner2", toLayer: "top" },
{ x: 1.27, y: 3.7 },
{ x: 2.07, y: 3.4 },
{ x: 2.27, y: 3.1 },
{ x: 2.17, y: 2.8 },
".C_VIO > .pin1",
]} routingPhaseIndex={null} />
<trace name="TEMP_SDA_PULLUP_VIO" from=".R_TEMP_SDA > .pin2" to=".R_TEMP_SCL > .pin2"
thickness="0.15mm" pcbPathRelativeTo=".R_TEMP_SDA > .pin2" pcbPath={[
{ x: 0.03, y: 0.4 },
{ x: -0.67, y: 0.4 },
{ x: -0.97, y: -0.2 },
".R_TEMP_SCL > .pin2",
]} routingPhaseIndex={null} />
<trace name="TEMP_SCL_PULLUP_VIO" from=".R_TEMP_SCL > .pin2" to=".C_VIO > .pin1"
thickness="0.15mm" pcbPathRelativeTo=".R_TEMP_SCL > .pin2" pcbPath={[
{ x: 2.33, y: -1.1 },
{ x: 2.63, y: -1.1 },
{ x: 2.83, y: -1.0 },
{ x: 3.33, y: 0.5 },
".C_VIO > .pin1",
]} routingPhaseIndex={null} />
{false && <>
<trace name="TEMP_SCL_SIGNAL" from=".U_MCU > .I2C_SCL" to=".U_TEMP > .SCL"
thickness="0.15mm" pcbPathRelativeTo=".U_MCU > .I2C_SCL" pcbPath={[
{ x: 0.4, y: -2.1 },
{ x: 0.4, y: -2.1, via: true, fromLayer: "bottom", toLayer: "top" },
{ x: 0.4, y: -2.1 },
{ x: 0.3, y: -0.3 },
{ x: 0.5, y: 0.1 },
{ x: 0.4, y: 1.2 },
{ x: 0.0, y: 1.5 },
".U_TEMP > .SCL",
]} routingPhaseIndex={null} />
<trace name="TEMP_SCL_PULLUP" from=".R_TEMP_SCL > .pin1" to=".U_TEMP > .SCL"
thickness="0.15mm" pcbPathRelativeTo=".R_TEMP_SCL > .pin1" pcbPath={[
{ x: -0.83, y: 0.6 },
".U_TEMP > .SCL",
]} routingPhaseIndex={null} />
{false && <>
<trace name="TEMP_SDA_SIGNAL" from=".U_MCU > .I2C_SDA" to=".U_TEMP > .SDA"
thickness="0.15mm" pcbPathRelativeTo=".U_MCU > .I2C_SDA" pcbPath={[
{ x: 0.2, y: -2.2 },
{ x: 0.3, y: -2.3 },
{ x: 0.3, y: -2.3, via: true, fromLayer: "bottom", toLayer: "top" },
{ x: 0.3, y: -2.3 },
{ x: 0.3, y: -0.7 },
{ x: 0.9, y: 1.3 },
".U_TEMP > .SDA",
]} routingPhaseIndex={null} />
<trace name="TEMP_SDA_PULLUP" from=".R_TEMP_SDA > .pin1" to=".U_TEMP > .SDA"
thickness="0.15mm" pcbPathRelativeTo=".R_TEMP_SDA > .pin1" pcbPath={[
{ x: -1.83, y: 1.0 },
{ x: -2.73, y: 1.0 },
{ x: -2.83, y: 1.1 },
".U_TEMP > .SDA",
]} routingPhaseIndex={null} />
</>}
</>}
{false && <>
<trace name="TEMP_SENSOR_GND" from=".U_TEMP > .GND" to=".U_MCU > .GND"
thickness="0.15mm" pcbPathRelativeTo=".U_TEMP > .GND" pcbPath={[
{ x: 0.35, y: 0.2 },
{ x: 0.25, y: 0.3 },
{ x: 0.25, y: 0.7 },
{ x: 0.55, y: 1.0 },
{ x: 0.55, y: 1.0, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: 0.55, y: 1.0 },
".U_MCU > .GND",
]} routingPhaseIndex={null} />
<trace name="TEMP_ADD0_GND" from=".U_TEMP > .ADD0" to=".U_MCU > .GND"
thickness="0.15mm" pcbPathRelativeTo=".U_TEMP > .ADD0" pcbPath={[
{ x: -0.15, y: 0.7 },
{ x: -0.15, y: 0.7, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: -0.15, y: 0.7 },
".U_MCU > .GND",
]} routingPhaseIndex={null} />
<trace name="TEMP_CAP_GND" from=".C_TEMP > .pin2" to=".U_MCU > .GND"
thickness="0.15mm" pcbPathRelativeTo=".C_TEMP > .pin2" pcbPath={[
{ x: 0.63, y: -0.3 },
{ x: 0.63, y: -0.3, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: 0.63, y: -0.3 },
".U_MCU > .GND",
]} routingPhaseIndex={null} />
</>}
</>}
<>
<trace name="TEMP_SCL_MCU_FINAL" from=".U_MCU > .I2C_SCL" to=".R_TEMP_SCL > .pin1"
schDisplayLabel="TEMP_SCL" thickness="0.15mm" routingPhaseIndex={1} />
<trace name="TEMP_SCL_SENSOR_FINAL" from=".U_TEMP > .SCL" to=".R_TEMP_SCL > .pin1"
schDisplayLabel="TEMP_SCL" thickness="0.15mm" pcbPathRelativeTo=".U_TEMP > .SCL" pcbPath={[
{ x: 0.35, y: -0.3 },
{ x: 0.25, y: -0.2 },
{ x: 0.0, y: 0.2 },
{ x: 0.0, y: 1.0 },
{ x: 0.35, y: 1.35 },
".R_TEMP_SCL > .pin1",
]} routingPhaseIndex={null} />
<trace name="TEMP_SDA_MCU_FINAL" from=".U_MCU > .I2C_SDA" to=".U_TEMP > .SDA"
schDisplayLabel="TEMP_SDA" thickness="0.15mm" routingPhaseIndex={1} />
<trace name="TEMP_SDA_PULLUP_FINAL" from=".R_TEMP_SDA > .pin1" to=".U_MCU > .I2C_SDA"
schDisplayLabel="TEMP_SDA" thickness="0.15mm" routingPhaseIndex={1} />
<trace name="TEMP_SDA_PULLUP_VIO_FINAL" from=".R_TEMP_SDA > .pin2" to=".R_BOOT > .pin1"
schDisplayLabel="VIO" thickness="0.15mm" routingPhaseIndex={1} />
{false && <trace name="TEMP_SCL_PULLUP_VIO_FINAL" from=".R_TEMP_SCL > .pin2" to=".C_VIO > .pin1"
thickness="0.15mm" pcbPathRelativeTo=".R_TEMP_SCL > .pin2" pcbPath={[
{ x: 2.33, y: -1.1 },
{ x: 2.63, y: -1.1 },
{ x: 2.83, y: -1.0 },
{ x: 3.33, y: 0.5 },
".C_VIO > .pin1",
]} routingPhaseIndex={null} />}
<trace name="TEMP_SENSOR_LOCAL_VIO_FINAL" from=".C_TEMP > .pin1" to=".U_TEMP > .V_POS"
schDisplayLabel="VIO" thickness="0.15mm" pcbPathRelativeTo=".C_TEMP > .pin1" pcbPath={[
{ x: -0.53, y: -0.8 },
{ x: -0.53, y: -1.2 },
{ x: -0.23, y: -1.5 },
".U_TEMP > .V_POS",
]} routingPhaseIndex={null} />
{false && <trace name="TEMP_SENSOR_VIO_FEED_FINAL_OLD" from=".C_TEMP > .pin1" to=".C_3V3_BULK > .pin1"
thickness="0.15mm" pcbPathRelativeTo=".C_TEMP > .pin1" pcbPath={[
{ x: 0.77, y: 1.8 },
{ x: 0.77, y: 1.8, via: true, fromLayer: "top", toLayer: "inner1" },
{ x: 0.77, y: 1.8 },
{ x: -0.43, y: -1.8 },
{ x: -5.03, y: -5.8 },
{ x: -5.83, y: -5.8 },
{ x: -5.83, y: -5.8, via: true, fromLayer: "inner1", toLayer: "bottom" },
{ x: -5.83, y: -5.8 },
".C_3V3_BULK > .pin1",
]} routingPhaseIndex={null} />}
<trace name="TEMP_SENSOR_PULLUP_VIO_LOCAL_FINAL" from=".C_TEMP > .pin1" to=".R_TEMP_SCL > .pin2"
schDisplayLabel="VIO" thickness="0.15mm" pcbPathRelativeTo=".C_TEMP > .pin1" pcbPath={[
{ x: 0.02, y: 0.4 },
{ x: 0.87, y: 0.9 },
{ x: 1.47, y: 0.9 },
".R_TEMP_SCL > .pin2",
]} routingPhaseIndex={null} />
<trace name="TEMP_SCL_PULLUP_VIO_FINAL" from=".R_TEMP_SCL > .pin2" to=".C_VIO > .pin1"
schDisplayLabel="VIO" thickness="0.15mm" pcbPathRelativeTo=".R_TEMP_SCL > .pin2" pcbPath={[
{ x: 0.38, y: 1.75 },
".C_VIO > .pin1",
]} routingPhaseIndex={null} />
{false && <trace name="TEMP_SCL_PULLUP_LOCAL_VIO_OLD" from=".U_TEMP > .V_POS" to=".R_TEMP_SCL > .pin2"
thickness="0.15mm" pcbPathRelativeTo=".U_TEMP > .V_POS" pcbPath={[
{ x: -0.35, y: 0.2 },
{ x: 0.15, y: 0.7 },
{ x: 0.15, y: 1.1 },
{ x: 0.35, y: 1.4 },
{ x: 0.85, y: 1.4 },
".R_TEMP_SCL > .pin2",
]} routingPhaseIndex={null} />}
<trace name="TEMP_SENSOR_GND_FINAL" from=".U_TEMP > .GND" to="net.GND"
schDisplayLabel="GND" thickness="0.15mm" pcbPathRelativeTo=".U_TEMP > .GND" pcbPath={[
{ x: 0.35, y: 0.2 },
{ x: 0.25, y: 0.3 },
{ x: 0.25, y: 0.7 },
{ x: 0.55, y: 1.0 },
{ x: 0.6, y: 1.0 },
]} routingPhaseIndex={null} />
<trace name="TEMP_ADD0_GND_FINAL" from=".U_TEMP > .ADD0" to=".C_TEMP > .pin2"
schDisplayLabel="GND" thickness="0.15mm" pcbPathRelativeTo=".U_TEMP > .ADD0"
pcbPath={[".C_TEMP > .pin2"]} routingPhaseIndex={null} />
<trace name="TEMP_CAP_GND_FINAL" from=".C_TEMP > .pin2" to=".U_MCU > .GND"
schDisplayLabel="GND" thickness="0.15mm" pcbPathRelativeTo=".C_TEMP > .pin2" pcbPath={[
{ x: 0.68, y: 0.0 },
{ x: 0.68, y: 0.0, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: 0.68, y: 0.0 },
".U_MCU > .GND",
]} routingPhaseIndex={null} />
<>
<trace name="STATUS_LED_DECOUPLING_FINAL" from=".D_STATUS > .VDD" to=".C_STATUS > .pin1"
schDisplayLabel="VIO" thickness="0.15mm" pcbPathRelativeTo=".D_STATUS > .VDD" pcbPath={[
{ x: -1.05, y: 0.6 },
{ x: -1.05, y: 0.6, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: -1.05, y: 0.6 },
".C_STATUS > .pin1",
]} routingPhaseIndex={null} />
<trace name="STATUS_LED_SIGNAL_FINAL" from=".U_MCU > .STATUS_LED" to=".D_STATUS > .DIN"
schDisplayLabel="STATUS_LED" thickness="0.15mm" routingPhaseIndex={1} />
<trace name="STATUS_LED_VIO_FINAL" from=".D_STATUS > .VDD" to=".C_3V3_BULK > .pin1"
schDisplayLabel="VIO" thickness="0.15mm" routingPhaseIndex={1} />
<trace name="STATUS_LED_GND_LOCAL_FINAL" from=".D_STATUS > .GND" to="net.GND"
schDisplayLabel="GND" thickness="0.15mm" pcbPathRelativeTo=".D_STATUS > .GND"
pcbPath={[
{ x: 0.15, y: -1.3 },
{ x: 0.15, y: -1.3, via: true, fromLayer: "top", toLayer: "bottom" },
]} routingPhaseIndex={null} />
<trace name="STATUS_LED_GND_FINAL" from=".C_STATUS > .pin2" to="net.GND"
schDisplayLabel="GND" thickness="0.15mm" pcbPathRelativeTo=".C_STATUS > .pin2"
pcbPath={[
{ x: -0.3, y: 0.2 },
{ x: -0.3, y: 0.2, via: true, fromLayer: "bottom", toLayer: "top" },
]} routingPhaseIndex={null} />
</>
</>
{/* Added after the released electrical layout so the frozen default-router
port identities remain stable. This local VM bypass shares the nearby
full-stack VS via and returns to the existing ground-plane fanout. */}
<C name="C_VM_LOCAL" value="100nF_50V_0402" layer="bottom"
pcbX={-3.0} pcbY={-4.5} pcbRotation={0}
schSectionName={sections.driverCore} schSheetName={sheets.driver}
schX={-8} schY={3} schRotation={-90} />
<trace name="VM_LOCAL_BYPASS" from=".U_DRV > .VS1" to=".C_VM_LOCAL > .pin1"
thickness="0.28mm" pcbPathRelativeTo=".U_DRV > .VS1"
pcbPath={[
{ x: -2.5, y: -1.86 },
{ x: -2.975, y: -2.55 },
{ x: -2.975, y: -2.55, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: -2.975, y: -2.55 },
]} routingPhaseIndex={null} />
<trace name="VM_LOCAL_GND" from=".C_VM_LOCAL > .pin2" to="net.GND"
thickness="0.2mm" pcbPathRelativeTo=".C_VM_LOCAL > .pin2"
pcbPath={[
{ x: -0.51, y: -0.7 },
{ x: 1.0, y: -0.7 },
{ x: 1.0, y: -0.7, via: true, fromLayer: "bottom", toLayer: "top" },
]} routingPhaseIndex={null} />
<C0201 name="C_VIO_LOCAL" layer="bottom"
pcbX={1.0} pcbY={1.3} pcbRotation={0}
schSectionName={sections.driverCore} schSheetName={sheets.driver}
schX={-4.2} schY={-2} schRotation={-90} />
<trace name="VIO_LOCAL_BYPASS" from=".U_DRV > .VCC_IO" to=".C_VIO_LOCAL > .pin1"
thickness="0.2mm" pcbPathRelativeTo=".U_DRV > .VCC_IO"
pcbPath={[
{ x: 1.5, y: 2.5 },
{ x: 1.5, y: 2.5, via: true, fromLayer: "top", toLayer: "bottom" },
{ x: 1.5, y: 2.5 },
".C_VIO_LOCAL > .pin1",
]} routingPhaseIndex={null} />
<trace name="VIO_LOCAL_GND" from=".C_VIO_LOCAL > .pin2" to="net.GND"
thickness="0.2mm" pcbPathRelativeTo=".C_VIO_LOCAL > .pin2"
pcbPath={[
{ x: -0.3, y: -1.1 },
{ x: -0.3, y: -1.1, via: true, fromLayer: "bottom", toLayer: "top" },
]} routingPhaseIndex={null} />
<C name="C_LDO_IN_LOCAL" value="2.2uF_25V_0402" layer="bottom"
pcbX={8.5} pcbY={6.0} pcbRotation={180}
schSectionName={sections.logicPower} schSheetName={sheets.power}
schX={3} schY={-6.8} schRotation={-90} />
<trace name="LDO_IN_LOCAL_BYPASS" from=".C_LDO_IN_LOCAL > .pin1" to=".U_3V3 > .VIN"
thickness="0.25mm" pcbPathRelativeTo=".C_LDO_IN_LOCAL > .pin1"
pcbPath={[".U_3V3 > .VIN"]} routingPhaseIndex={null} />
<trace name="LDO_IN_LOCAL_GND" from=".C_LDO_IN_LOCAL > .pin2" to="net.GND"
thickness="0.2mm" pcbPathRelativeTo=".C_LDO_IN_LOCAL > .pin2"
pcbPath={[
{ x: -0.86, y: 0.4 },
{ x: -0.86, y: 2.2 },
{ x: -0.7, y: 2.7 },
{ x: -0.7, y: 2.7, via: true, fromLayer: "bottom", toLayer: "top" },
]} routingPhaseIndex={null} />
<C1uF0201 name="C_LDO_OUT" layer="bottom"
pcbX={6.1} pcbY={4.6} pcbRotation={180}
schSectionName={sections.logicPower} schSheetName={sheets.power}
schX={8} schY={-6.8} schRotation={-90} />
<trace name="LDO_OUT_BYPASS" from=".C_LDO_OUT > .pin1" to=".U_3V3 > .VOUT"
thickness="0.25mm" pcbPathRelativeTo=".C_LDO_OUT > .pin1"
pcbPath={[
{ x: 0.3, y: -0.03 },
{ x: 0.19, y: 1.6 },
{ x: -0.45, y: 1.6 },
".U_3V3 > .VOUT",
]} routingPhaseIndex={null} />
<trace name="LDO_OUT_GND" from=".C_LDO_OUT > .pin2" to="net.GND"
thickness="0.2mm" pcbPathRelativeTo=".C_LDO_OUT > .pin2"
pcbPath={[
{ x: -0.2, y: 0.59 },
{ x: -0.2, y: 0.59, via: true, fromLayer: "bottom", toLayer: "top" },
]} routingPhaseIndex={null} />
{/* Appended after the frozen release routing to preserve every existing
component/port identity. This through-via sits wholly inside the
large TVS anode land and connects it directly to the GND plane. */}
<via name="D_VM_TVS_GND_VIA" pcbX={2.4} pcbY={3.4}
fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.45mm"
connectsTo="net.GND" />
{motorMountingHoles.map(({ name, x, y }) => (
<MotorMountingHole key={name} name={name} x={x} y={y} />
))}
<silkscreentext text="PWR" layer="top" pcbX={-5.3} pcbY={-7.2} pcbRotation={90}
fontSize="0.75mm" isKnockout knockoutPadding="0.12mm" />
<silkscreentext text="DATA" layer="top" pcbX={-5.3} pcbY={7.2} pcbRotation={270}
fontSize="0.75mm" isKnockout knockoutPadding="0.12mm" />
<silkscreentext text="MOTOR" layer="top" pcbX={-8.8} pcbY={0} pcbRotation={270} fontSize="0.5mm" />
<silkscreentext text="A+ A- B+ B-" layer="top" pcbX={-5.8} pcbY={0} pcbRotation={270} fontSize="0.4mm" />
<silkscreentext text="BOOT" layer="top" pcbX={8.8} pcbY={5.0} fontSize="0.45mm" />
<silkscreentext text="NEMA8 20x20 4L" layer="bottom" pcbX={0} pcbY={-8.8} pcbRotation={180} fontSize="0.5mm" />
<silkscreentext text="0.60A MAX" layer="bottom" pcbX={0} pcbY={8.8} fontSize="0.5mm" />
{/* Non-electrical locator for assembly.cable. The real J_MOTOR remains
the unchanged, routed JLCPCB part above; this zero-copper endpoint
only gives the assembly renderer its JST-SH-4 mating position. */}
<connector
name="J_MOTOR_ASSEMBLY_ENDPOINT"
standard="jst_sh"
pinCount={4}
pcbX={-7.6}
pcbY={0}
pcbRotation={270}
noSchematicRepresentation
doNotPlace
cadModel={null}
noConnect={["pin1", "pin2", "pin3", "pin4"]}
footprint={
<footprint insertionDirection="from_above">
<courtyardoutline outline={[
{ x: -3.654997, y: 2.3539963 },
{ x: 3.652203, y: 2.3539963 },
{ x: 3.652203, y: -2.3370037 },
{ x: -3.654997, y: -2.3370037 },
{ x: -3.654997, y: 2.3539963 },
]} />
</footprint>
}
/>
</board>
</assembly.device>
)
}
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