pixalynx/cm5-minimal-carrier

docs/minima-comparison.md

# CM5 MINIMA comparison and revision B changes

Reviewed 18 September 2026 against [piecol/CM5_MINIMA_REV2](https://github.com/piecol/CM5_MINIMA_REV2/tree/e9dbac2df2d8a7606cb91eae80b1b3b740250910), commit `e9dbac2df2d8a7606cb91eae80b1b3b740250910` (28 March 2025). The KiCad schematic was exported to an XML netlist and compared with our generated electrical intent; the PCB was inspected separately. Reproduce the extraction with `scripts/review-minima.py` using KiCad's Python. The extracted facts and source hashes are in `references/minima-comparison.json`.

The checkout in `references/external/CM5_MINIMA_REV2` retains its CERN-OHL-S-2.0 licence. No upstream layout, routing or software was transplanted into our design. Raspberry Pi's official CM5 documentation remains the primary electrical/mechanical reference.

## What the reference tells us

| Topic | Reference evidence | Decision for our carrier |
|---|---|---|
| Main power | J101 VBUS connects directly to all six CM5 5 V contacts. CC1/CC2 run directly to module pins 94/96. | Our PD architecture agrees. Keep the on-module controller and avoid duplicate Rd resistors. |
| HDMI mapping | All 12 used HDMI0 signals connect to the same HDMI Type-A pins as our board. | Independently corroborates the mapping already verified against Raspberry Pi. |
| HDMI protection | D401–D403 use PUSB3F96X; U405 is STMPS2151STR. NC lands are explicitly assigned to their corresponding signal nets. | Retain our documented TI arrays and official-reference RT9742 switch; these are different parts, not footprint-compatible substitutions. Preserve the explicit copper bridges across TI NC lands. |
| USB protection | D101 protects the input connector's USB D+/D− lines, which are also used for programming. | It is not a missing CC protection circuit. Our power-only USB-C has no USB data wiring, as requested. |
| Stack-up | The reference is six-layer; its `100ohm` net class uses 0.13 mm width / 0.25 mm gap. | Do not transfer these dimensions to our four-layer board. Calculate against our own stack-up. |
| Debug access | Six named power/ground test points are present. | Add six bare bottom-side probe pads for bring-up without increasing the 15-part assembly BOM. |
| Boot/programming | Input USB data and a boot-mode switch support in-place programming. | Keep the original pre-programmed, non-wireless eMMC assumption. Adding that functionality would expand this V1's scope. |

The open [HDMI Power-on Glitch issue #2](https://github.com/piecol/CM5_MINIMA_REV2/issues/2) describes a restart failure with HDMI connected under particular supply/cable combinations. The report does not establish a root cause or a hardware fix. It is a useful regression scenario, not evidence that a capacitor or switch substitution will cure it.

## Changes implemented

1. **Corrected a manufacturing origin mismatch.** Revision A's CPL used bottom-left board coordinates, while its Gerbers/drills used KiCad absolute coordinates. All revision B outputs now use KiCad `(68,130)`, corresponding to tsCircuit `(-32,-30)`, as the common origin. The final outline is `(0,0)` to `(64,60)` mm. Bottom components retain the same top-view coordinate frame.
2. **Recalculated HDMI geometry with JLC's current calculator.** For JLC04161H-3313, 1 oz outer / 0.5 oz inner copper, L1 referenced to L2, solder-masked non-coplanar differential pairs and a requested 0.23 mm gap, the 100 Ω result is **0.1234 mm width / 0.2301 mm gap**. These are now the straight-run route parameters. The calculator's 0.5% search tolerance is not a manufacturing guarantee. `lib/stackup.json` records the complete observation.
3. **Added probe pads TP1–TP6.** Input VBUS, module-side 5 V, 3.3 V output, HDMI 5 V and two grounds are accessible from underneath. No test branches were added to TMDS or CC. Pads have no paste and are excluded from the assembly BOM/CPL.
4. **Made fabrication settings explicit.** ENIG, green mask, 0.03 mm component-pad mask expansion, 0.10 mm minimum nominal mask web, and tenting on both sides of every through-via are recorded. Labels are at least 1 mm high; silk lines/text strokes are 0.15 mm.
5. **Added export-level checks and an electrical-test netlist.** The build validates the common origin, pad coordinates, paste exclusions, routed plated slots, NPTH holes, tenting and mask webs from the actual output files. IPC-D-356 provides a named-net electrical-test reference. Hashes tie these checks to the reviewed files.

The design-rule trace floor is now 0.12 mm to accommodate the manufacturer's 0.1234 mm calculation; the previous 0.127 mm floor was a project setting. Clearances, via rules and DRC exclusions have not been relaxed. JLC publishes 3.5 mil multilayer trace/space capability; order-specific manufacturability must still be confirmed.

## What this does not establish

- **Fabricator approval:** JLC still needs to confirm the chosen stack-up, 100 Ω ±10% coupon requirement and final CAM treatment. The calculator does not model connector/ESD transitions or the complete HDMI channel.
- **Assembler approval:** live stock, exact library centroid/rotation registration, solder paste/stencil process, two-sided assembly and connector stakes remain open. The revised CPL has a correct common coordinate origin but is still labelled `REVIEW`.
- **Physical operation:** USB-C attach/inrush, connector current/temperature, HDMI hot-plug/restart, ESD, cooling and exact purchased-connector enclosure fit require hardware evidence. The HDMI visual model remains a proxy.

Revision B is a stronger prototype review package, not a signed fabrication or production release. See [order notes](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/docs/jlcpcb-order-notes.md) and the [release checklist](https://tscircuit.com/pixalynx/cm5-minimal-carrier/blob/docs/fabrication-checklist.md).

Sources: [JLC impedance calculator](https://jlcpcb.com/pcb-impedance-calculator), [stack-ups](https://jlcpcb.com/impedance), [CPL specification](https://jlcpcb.com/help/article/pick-place-file-for-pcb-assembly), [PCB capabilities](https://jlcpcb.com/capabilities/Capab), [KiCad export options](https://docs.kicad.org/10.0/en/cli/cli.html).