pixalynx/cm5-minimal-carrier

docs/hdmi-layout.md

# HDMI and PCB routing

## Electrical mapping

| Function | Official CM5 pin | Carrier J2 local pin | HDMI J4 pin |
|---|---:|---:|---:|
| TX2 P / N | 170 / 172 | 70 / 72 | 1 / 3 |
| TX1 P / N | 176 / 178 | 76 / 78 | 4 / 6 |
| TX0 P / N | 182 / 184 | 82 / 84 | 7 / 9 |
| Clock P / N | 188 / 190 | 88 / 90 | 10 / 12 |
| CEC | 151 | 51 | 13 |
| DDC SCL | 200 | 100 | 15 |
| DDC SDA | 199 | 99 | 16 |
| HPD | 153 | 53 | 19 |
| +5 V | Through U1 | — | 18 |
| Ground | All CM5 GND contacts | See pin audit | 2, 5, 8, 11, 17 and four shield stakes |
| Utility / HEAC | Unused | — | 14 NC |

CM5 already includes the DDC pull-ups, CEC pull-up, HPD pull-down and appropriate signal interfacing. This carrier adds no extra I²C level shifter or TMDS AC coupling capacitor. CM5 HDMI0 is selected as the primary display port.

## ESD implementation

U2 and U3 are genuine TI TPD4E05U06DQAR, approximately 0.5 pF channel capacitance, intended for HDMI 2.0. Each package protects two differential pairs. U4 protects CEC, DDC SDA/SCL and HPD. Ground pins 3/8 connect to adjacent ground vias. The arrays are close to the HDMI connector, with the signal route passing through their lands.

The DQA device's pins 6/7/9/10 are **NC**, not internally connected pass-through outputs. Each protected pin 1/2/4/5 is joined in PCB copper to opposite NC land 10/9/7/6. That copper connection is explicitly present and independently continuity-checked. There are no ESD branches or testpoint stubs on the TMDS nets.

## Routed lengths

Lengths are drawn copper centreline lengths between socket and HDMI pad centres, including the external ESD land bridges. They do not include connector contact or on-module electrical lengths.

| Pair | P length (mm) | N length (mm) | Skew (mm) | Signal vias |
|---|---:|---:|---:|---:|
| TX2 | 13.4701 | 13.4701 | 0.0000 | 0 |
| TX1 | 13.5944 | 13.5944 | 0.0000 | 0 |
| TX0 | 13.7186 | 13.7186 | 0.0000 | 0 |
| CLK | 13.8429 | 13.8429 | 0.0000 | 0 |

The current build recalculates these values in `output/validation.json`. Raspberry Pi's maximum within-pair mismatch is 0.15 mm and the inter-pair allowance is 25 mm. The present inter-pair spread is approximately 0.373 mm. Equal source polylines are not a substitute for connector/package/channel signal-integrity evaluation.

## Stack-up and impedance

Proposed controlled stack-up: **JLC04161H-3313**, nominal 1.6 mm finished, 1 oz outer copper and 0.5 oz inner copper. Published starting dimensions:

| Layer / dielectric | Material and role | Thickness |
|---|---|---:|
| L1 | Components, HDMI and other signals | 0.035 mm copper |
| L1–L2 | 3313 prepreg, published Dk 4.1 | 0.0994 mm |
| L2 | Continuous GND reference | 0.0152 mm copper |
| L2–L3 | Core | 1.265 mm |
| L3 | Continuous CM5_5V distribution | 0.0152 mm copper |
| L3–L4 | 3313 prepreg | 0.0994 mm |
| L4 | Slow controls and underside decoupling | 0.035 mm copper |

These published material dimensions are a starting specification, not a guaranteed measured finished board thickness. Obtain the manufacturer's confirmed stack-up and impedance coupon plan.

Target 100 Ω differential (request ±10% or better). The revision B geometry, calculated with JLC’s online tool on 18 September 2026, is **0.1234 mm conductor width and 0.2301 mm edge gap on straight coupled runs** (0.3535 mm centre spacing). The short socket, ESD and HDMI pad escapes necessarily open the pair; the shallow/45° bends also change local edge spacing. Those transitions need field-solver or signal-integrity review. tsCircuit does not enforce 100 Ω or calculate impedance from the laminate. The result uses the solder-masked, non-coplanar differential model, L1 over L2, 1 oz / 0.5 oz copper. The calculator returned width 0.1234 mm and spacing 0.2301 mm for a requested 0.23 mm gap. Its 0.5% search tolerance is numerical, not a fabrication tolerance. The current stack-up label states 1.56 mm ±10% finished thickness in the 1.6 mm order category. See `lib/stackup.json` for the recorded inputs/result.

Do not use default 7628 material for this geometry. Adjust pair width/spacing together after the JLC impedance calculation; regenerate and repeat clearance, skew and via checks. No adjacent coplanar ground flood is used on L1, so the intended model is coupled microstrip over L2. Do not add a top flood near these pairs without recalculating impedance.

L2 contains no signal tracks and no power split. The ground plane is independently filled as one connected region. TMDS is on L1 throughout; it never changes reference planes. Module ground contacts and ESD ground pads have short ground escapes; all connector shields are bonded. L3 may have antipads for unrelated through-vias, but it is not the HDMI reference plane.

## Acceptance beyond DRC

Confirm 100 Ω with JLC's solver/coupon; inspect pad-neck and ESD transitions; verify no return-plane void under any TMDS segment in final CAM output; review the complete CM5/socket/ESD/cable channel. Bring up at 1080p60, then test the intended highest display mode, cable lengths, EDID/DDC, hot-plug and CEC. CM5's HDMI 2.0 capability is not a claim that this unbuilt carrier has passed a 4Kp60 eye test.