muse/book-reading-clip-lamp

verify-release.py

"""Fail on circuit errors; audit indicator polarity, via sizes and Seeed interface."""
import json
from pathlib import Path
p=Path(__file__).parent
d=json.loads((p/'dist/index/circuit.json').read_text())
errors=[x for x in d if x.get('error_type') or x['type'].endswith('_error')]
assert not errors,errors
components={x['name']:x for x in d if x['type']=='source_component'}
nets={x['source_net_id']:x['name'] for x in d if x['type']=='source_net'}
for ref,sku,anode,cathode in [('LED7','C965805','V3V3','STATUS_A'),('LED8','C965800','CHG_LED_A','CHG_N')]:
 c=components[ref];assert c['supplier_part_numbers']['jlcpcb']==[sku],(ref,c)
 ports=[x for x in d if x['type']=='source_port' and x['source_component_id']==c['source_component_id']]
 pc=next(x for x in d if x['type']=='pcb_component' and x['source_component_id']==c['source_component_id'])
 coords={}
 for number,alias,net in [(1,'cathode',cathode),(2,'anode',anode)]:
  port=next(x for x in ports if x.get('pin_number')==number)
  assert alias in port['port_hints'],(ref,port)
  actual={nets[n] for t in d if t['type']=='source_trace' and port['source_port_id'] in t['connected_source_port_ids'] for n in t.get('connected_source_net_ids',[])}
  assert actual=={net},(ref,number,actual)
  pp=next(x for x in d if x['type']=='pcb_port' and x.get('source_port_id')==port['source_port_id']);coords[number]=pp['x']
 assert coords[1]>coords[2],(ref,coords)
 assert any(x['type']=='cad_component' and x['pcb_component_id']==pc['pcb_component_id'] for x in d),ref
vias=[x for x in d if x['type']=='pcb_via']
assert vias and all(x['hole_diameter']==0.3 and x['outer_diameter']==0.45 for x in vias)
print('PASS: zero circuit error records; explicit LED supplier parts, cathode/anode net mappings, physical pad orientation, CAD models and 0.30/0.45 mm vias')

# Camera audit rejects unsafe rail, AF ground, translator direction and core wiring.
exec(compile((p/'verify-camera-interface.py').read_text(),str(p/'verify-camera-interface.py'),'exec'))