muse/book-reading-clip-lamp

routing-notes.txt

M10 CHARGER DETECTION ROUTING — 12 October 2026
Current saved input includes U14-U18 and their support parts; obsolete R1/R2
CC resistors are removed. Retained 259 baseline routes after matching named
nets, pad coordinates/layers and checking new obstacles. Routed/repaired 93
paths with work-routing-m10/route-additions.mjs. The current capture is input
only; its zero route count is not the final result. See routingProfile in
saved-routing-provenance.json for final hashes and counts.

352 replay routes + three explicit thermal links = 355 compiled traces;
438 vias. All via holes/pads remain 0.30/0.45 mm. Rotated USB plated slots,
NPTH clearance and reserved unchanged IC escapes are included in routing.
Exact wire/via joins prevent microscopic geometry segments. Full normal build,
input guard and all-layer Gerber shorts pass. Camera bus timing, USB impedance,
power copper, via-in-pad fabrication and bench operation remain qualification
items. Earlier revision descriptions below are historical, not current counts.

09 October 2026 — M8 M3 PCB mounts
Shared four mount axes with 3.2 mm NPTH and 3 mm-radius surface keepouts.
Moved R5/R8/R23/R19/C37/U12/C29. Incremental replay snapshot regenerated from
actual core input; rerouted affected connections. Invalid translated IC escapes
were discarded during DRC review and freshly routed with a 0.05 mm grid after
ripping up blocking neighbours. LED_LINK_4 has an explicit reviewed USB shell
pad detour in routing-replacements.json. No checks or clearance rules disabled.
Build error records: 0. Gerber shorts: none on top/bottom, inner1 and inner2.
Mounting checks: drill/post axes agree; surface copper clear; internal trace
clearance >=0.225 mm from mounting drill edge. Physical prototype still needed.

SAVED ROUTING — REMOVABLE HEAD HARNESS M6

The default build imports reviewed routes through the documented custom
algorithmFn interface. Core imports the copper and runs its normal DRC.
Independent Gerber shorts checks cover all four layers. No errors are suppressed.

saved-routing-input.json captures J3's eight-pin imported JST header, the
removed J4 lands, and moved Light switch/passives. The full geometry/net/drill
replay guard is unchanged. Never weaken it to reuse an obsolete snapshot.

The current snapshot combines 286 endpoint/net-checked preserved routes with
25 newly connected routes. work-routing-m6 contains the original baseline,
endpoint mapper, changed-obstacle pruning and 0.1 mm incremental routing script.
Two short amplifier IC escapes are reused only at unchanged pad coordinates.
New vias use 0.30 mm drills / 0.45 mm pads; normal core DRC and shorts apply.
routing-replacements.json explicitly combines two adjacent same-net SPK_N vias
into one physical through via at the original amplifier escape coordinate.
It records both the full original and replacement paths and a reviewed reason.

Imported pin 1 was an equal-width/equal-height pill with a square pad. Core
0.0.1971 emits a null plated-hole ID for that representation. The explicit
circular_hole_with_rect_pad preserves the exact 0.9000236 mm drill and
1.6999966 mm square copper dimensions. Input recapture confirms identical
net endpoints and all obstacle coordinates/dimensions; identities are corrected.
The new capture is used without modifying the replay guard or disabling DRC.

The browser and CLI serializers differ in tiny trigonometric rounding,
redundant via aliases and explicitly emitted defaults. Comparison therefore
rounds numbers to 9 decimal places in millimetres, compares named-net bindings
for obstacles, canonicalizes connectivity sets, and materializes the 0.2 mm
trace-to-hole default. Exact pad IDs and coordinates remain checked in the
connection list. saved-routing-holes.json records actual non-plated drill IDs
and geometry so browser-only hole metadata is compared consistently. Changed
geometry, named nets or clearance rules still fail.
verify-routing-guard.ts exercises these cases, including rejected 0.01 mm moves.

Full replacements apply first; via corrections apply afterwards and must match
the resulting path. Every replacement still needs normal clearance/short checks.
The provenance file distinguishes the unrouted input capture from the final
geometry repair and records its routing rules.

After changing component positions, footprints, nets or routing constraints:
1. Run bun run typecheck and all netlist/schematic/placement checks.
2. Run bun run reroute. The CLI-only reroute.circuit.tsx entrypoint uses the normal
   local pipeline9 with fresh-routing.ts and refreshes dist/autorouter-debug.
   Its circuit output is dist/reroute/circuit.json. Browser previews load only
   the guarded saved-route replay, avoiding Node-only solver dependencies.
   Optional trace/via simplification is omitted; detailed paths are retained. Normal topology, detailed routing,
   global repairs, trace widths and all final core/short checks remain enabled.
3. Inspect the build log and copper. Run bun run capture-routing to import that
   geometry as source; this resets both previous via corrections and full route
   replacements, which cannot be safely reused across changed routes. Capturing does not mean the new route is valid.
4. Make any reviewed corrections, rebuild with bun run build, and run
   bun run check:shorts. Also check inner1 and inner2 explicitly.
5. Resolve every routing/short/placement error before sharing revised copper.
   Finish USB impedance, converter-loop, thermal and assembly reviews separately.

The delivered board is an engineering prototype, not an approved Gerber release.
The PCB SVG previews hide inner pours and fade other layers for readability;
dist/index/circuit.json contains the full four-layer geometry.

TOOLCHAIN UPDATE (08 October 2026)
tscircuit 0.0.2774 adds stricter routing/physical-hole checks. Three reviewed
local corrections are recorded in routing-replacements.json: move the C7/C9
GND detour 0.15 mm from the U3 SYS escape; add a bend in LED_LINK_4 beside the
lower-left mounting drill; bow the U4 ground trace around the acoustic hole.
All original terminal points, nets, via sizes and component positions remain.
J3 pin 1 explicitly sets both drill offsets to zero, preventing a non-finite
in-memory hole polygon in the new connectivity checker. Its dimensions stay
identical to the imported land pattern. No DRC checks or input guards are disabled.

VIA SIZE UPDATE (0.2.1)
Board minViaHoleDiameter=0.3 mm, minViaPadDiameter=0.45 mm. All explicit
vias and saved-route via points use those exact sizes. The four explicit-via
obstacles and saved routing rules were updated together; all center positions,
trace paths, nets and other clearances are unchanged. Normal input guarding,
core DRC and independent shorts remain enabled.

CLOUD BUILD DISCOVERY (0.2.4)
includeBoardFiles selects only index.circuit.tsx. mainEntrypoint alone does not
restrict automatic board discovery. The previous cloud build also discovered
reroute.circuit.tsx and timed out on that fresh-routing job after1200000 ms;
index.circuit.tsx itself completed successfully. Explicit bun run reroute
remains available, but its convergence and clean DRC are not guaranteed.

INDICATOR FIX (0.2.5)
JLC imports replace the generic status LEDs. Four route endpoints moved less
than0.03 mm, and their port IDs were remapped by original net/polarity. All
other routed paths remain unchanged. Actual updated input was recaptured,
and full parts-enabled build, placement, guard and Gerber shorts repeated.

SEEED 0.3.0 FINAL CHECK
Fresh routing took 881265 ms. LIGHT_KEY via correction is documented in
validation.txt and saved-routing-provenance.json. Final full build: 22.61 s,
zero errors; independent all-layer/inner1/inner2 Gerber shorts pass.