mohan-bee/stm32-midi-keys

Clips rectangular ground-region geometry to fit within the board’s scaled rounded-edge outline using polygon intersection.

Version
1.0.2
License
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COMPONENTS.md

PCBPCB preview for COMPONENTS.md
SchematicSchematic preview for COMPONENTS.md
# JLCPCB components

The native board instantiates **35 imported component modules across 66 placements**.
`jlcpcb-components.ts` imports the modules in `imports/`; the board selects them by
reference designator. `source/jlcpcb-bom.json` lists every manufacturer part number,
JLCPCB number, module, and placement. These are actual `tsci import --jlcpcb` outputs.

The board overrides each imported footprint with the source KiCad pad geometry and
keeps the original physical pad-to-net assignments. This preserves the requested
PCB layout while adding supplier/manufacturer data. Imported schematic symbols
are disabled for this PCB-only design. The imported 3D models have not been aligned
or verified against the footprint overrides.

Examples: U1 STM32F072CBT6 / C81720; U2 AP2112K-3.3TRG1 / C51118;
U3 USBLC6-2SC6 / C7519; Q1 AO3400A / C20917;
J1 TYPE-C-31-M-12 / C165948; J3/J4 S5B-PH-K-S(LF)(SN) / C157923.

Generic resistors/capacitors were selected by the source value and 0603 package.
The source does not specify their complete manufacturer/rating requirements.
Headers, LEDs, fuse, ferrite, switch suffix, and crystal are selected candidates,
not proof of the original assembly BOM. Full procurement equivalence is not claimed.

Y1 is an 8 MHz, 3225 four-pad, 10 pF load crystal (C400090). The importer omitted
the required `loadCapacitance`, so the module includes that catalog value explicitly.
The original 20 pF capacitors are preserved; effective crystal load with PCB stray
capacitance still needs electrical verification. The board explicitly permits a
50 mm crystal-net route ceiling because the preserved endpoint spacing exceeds
the native crystal primitive's default 10 mm limit. This is not signal-integrity
approval of that route length.

The capacitors explicitly set `maxDecouplingTraceLength={300}` because the
automatic 1 mm value incorrectly propagates to the entire shared supply net
(see `ISSUES.md`). Local decoupling quality is not validated by that override.

**Unassigned:** BZ1 is only specified as `Speaker/Piezo` with a 12 mm body and
7.6 mm pin pitch. No verified matching JLCPCB part was found; it retains its source
footprint without a fabricated supplier number. TK1–TK14, H1–H4, and JP1 are copper
electrodes, mounting holes, and a solder jumper, so they do not need purchased parts.

Run `python3 scripts/verify-jlcpcb.py` after building. It checks all 241 connected
physical pads against the original nets and checks all 66 supplier assignments.