imrishabh18/pcbgolf
A complete 4-layer PCBGolf controller PCB with STM32H7 MCU, USB/SD and CAN interfaces, power regulation, protection, connectors, switches, LEDs, clocking, and supporting passives.
- Version
- 1.6.1
- License
- unset
- Stars
- 0
source-corrections.json
{
"schemaVersion": 1,
"policy": "Retain source MPN and functional connectivity; correct the conflicting original footprint and package-specific pin numbering. Original files remain unmodified.",
"corrections": [
{
"id": "NCS20071SN2-package-and-pinout",
"references": [
"U9",
"U10",
"U11",
"U12"
],
"mpn": "NCS20071SN2T1G",
"datasheet": "https://www.onsemi.com/pdf/datasheet/ncs20071-d.pdf",
"datasheetRevision": "15, February 2026",
"evidencePages": {
"pinConnections": 3,
"orderingInformation": 4,
"packageDrawingCase483": 21
},
"originalSymbol": "pcbgolf:NCS20071XV",
"originalFootprint": "SOIC-8_3.9x4.9mm_P1.27mm",
"correctedValue": "NCS20071SN",
"correctedDescription": "Single operational amplifier, TSOP-5 / SOT-23-5, onsemi case 483",
"footprint": "SOT-23-5",
"footprintFile": "footprints/kicad/SOT-23-5.kicad_mod",
"modelFile": "3dmodels/SOT-23-5.step",
"templatePath": "/Applications/KiCad/KiCad.app/Contents/SharedSupport/footprints/Package_TO_SOT_SMD.pretty/SOT-23-5.kicad_mod",
"modelTemplatePath": "/Applications/KiCad/KiCad.app/Contents/SharedSupport/3dmodels/Package_TO_SOT_SMD.3dshapes/SOT-23-5.step",
"templateSha256": "455a3f7c3e5eb5b8847eaa5df23e18651e78ab9f75afd09a0883758a0d901761",
"bundledFootprintSha256": "ad2f63cd15495f5a97f59b64fa2b9d83d4a2d0bfa3cb9349a8e682fb0e064591",
"modelSha256": "720a6eab0024069bbee68e7cb4c3ff1149468a34611225cdc852662c5d0ec2b7",
"templateOrigin": "KiCad standard footprint library, KiCad 10 installed bundle; JEDEC MO-178 variation AA, 0.95 mm lead pitch",
"originalToActualPinMap": {
"1": "3",
"2": "2",
"3": "4",
"4": "1",
"5": "5"
},
"removedUnconnectedPads": [
"6",
"7",
"8"
],
"originalPinFunctions": {
"1": "IN+",
"2": "VSS",
"3": "IN-",
"4": "OUT",
"5": "VDD"
},
"actualPinFunctions": {
"1": "OUT",
"2": "VSS",
"3": "IN+",
"4": "IN-",
"5": "VDD"
},
"originalSymbolEvidence": "work/PCBGolf/pcbgolf_4.kicad_sch embedded NCS20071XV_1_1: pin1 input +, pin2 power V-, pin3 input -, pin4 output, pin5 power V+",
"rationale": "Source assigned an eight-pad SOIC footprint to a five-pin MPN while the schematic symbol used a different five-pin package pinout. The replacement retains the MPN and maps nets by function, removing only three nonexistent unconnected pads."
},
{
"id": "J3-USB4105-JLC-PTH-compatibility",
"type": "connector_replacement",
"references": [
"J3"
],
"originalMpn": "DX07S024XJ1R1100",
"mpn": "USB4105-GF-A",
"originalFootprint": "DX07S024XJ1R1100",
"footprint": "USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal",
"correctedValue": "USB4105-GF-A",
"correctedDescription": "USB 2.0 Type-C receptacle,16 contacts,SMT signal terminals,5 A,top mount,horizontal",
"datasheet": "https://gct.co/files/drawings/usb4105.pdf",
"specification": "https://gct.co/files/specs/usb4105-spec.pdf",
"productPage": "https://gct.co/connector/usb4105",
"footprintFile": "footprints/kicad/USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal.kicad_mod",
"modelFile": "3dmodels/USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal.step",
"templatePath": "/Applications/KiCad/KiCad.app/Contents/SharedSupport/footprints/Connector_USB.pretty/USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal.kicad_mod",
"modelTemplatePath": "/Applications/KiCad/KiCad.app/Contents/SharedSupport/3dmodels/Connector_USB.3dshapes/USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal.step",
"bundledFootprintSha256": "9cea98270e673c9f3e29a3badd21f0b54d280df4c272e0c17c3d729a1876658b",
"bundledModelSha256": "6338ce740fa231c2d3dcc6384e0576994a47240a312a21413cb85d76990a69a0",
"originalToActualPinMap": {
"A1": "A1",
"A4": "A4",
"A5": "A5",
"A6": "A6",
"A7": "A7",
"A8": "A8",
"A9": "A9",
"A12": "A12",
"B1": "B1",
"B4": "B4",
"B5": "B5",
"B6": "B6",
"B7": "B7",
"B8": "B8",
"B9": "B9",
"B12": "B12",
"B1T": "B1",
"B4T": "B4",
"B5T": "B5",
"B6T": "B6",
"B7T": "B7",
"B8T": "B8",
"B9T": "B9",
"B12T": "B12",
"S1B": "SH",
"S1T": "SH",
"S1TH": "SH",
"S2B": "SH",
"S2T": "SH",
"S2TH": "SH",
"S3B": "SH",
"S3T": "SH",
"S3TH": "SH",
"S4B": "SH",
"S4T": "SH",
"S4TH": "SH"
},
"removedUnconnectedPads": [
"A10",
"A11",
"A2",
"A3",
"B10",
"B10T",
"B11",
"B11T",
"B2",
"B2T",
"B3",
"B3T"
],
"internallyConnectedPinGroups": [
[
"A1",
"B12"
],
[
"A4",
"B9"
],
[
"A9",
"B4"
],
[
"A12",
"B1"
]
],
"newSharedShieldPin": "SH",
"physicalSolderLandNote": "16 contact pin records occupy12 unique SMT copper lands. Four power/ground A/B pairs share exact same copper; all4 plated shell slots use SH.",
"placement": {
"old": {
"x": 7.5,
"y": -16.2,
"rotation": 0
},
"new": {
"x": 7.5,
"y": -21,
"rotation": 0
},
"preservedExactPads": [],
"matingDirection": "from_bottom",
"matingFaceYmm": -24.675
},
"reason": "Source JAE signal annular rings and hole pitch do not meet standard JLC multilayer limits; source round shell holes also disagree with the JAE rectangular stakes/recommended slots.",
"footprintTemplateDelta": [
{
"pins": [
"A1",
"B12"
],
"kind": "smd",
"originalNativeCenterYmm": -3.68,
"correctedNativeCenterYmm": -3.6875,
"originalHeightMm": 1.15,
"correctedHeightMm": 1.135,
"trimmedEdge": "locator-facing end",
"reason": "Increase NPTH-to-GND copper gap above JLC0.20mm while retaining exact manufacturer mechanical-hole positions; retains over98% of recommended ground solder land area"
},
{
"pins": [
"A12",
"B1"
],
"kind": "smd",
"originalNativeCenterYmm": -3.68,
"correctedNativeCenterYmm": -3.6875,
"originalHeightMm": 1.15,
"correctedHeightMm": 1.135,
"trimmedEdge": "locator-facing end",
"reason": "Increase NPTH-to-GND copper gap above JLC0.20mm while retaining exact manufacturer mechanical-hole positions; retains over98% of recommended ground solder land area"
}
],
"templateSourceSha256": "3b8d7da3cae5114ec83022a759a78925113bc2eeec100ea447594f6d8687e4b8",
"nativeManufacturingRule": {
"type": "NPTH hole to copper",
"minimumMm": 0.2,
"scope": "J3",
"source": "https://jlcpcb.com/capabilities/Capabilities"
},
"status": "User-authorized and adopted; full native DRC has zero errors and unconnected items. Copper parity and source audit pass.",
"functionalPreservation": {
"USB": "USB2 Type-C reversible mating; A6/B6 D+,A7/B7 D-; allsourceSS pins are NC and removed",
"CC": "A5 CC1,B5 CC2 retained independently",
"power": "A4/A9/B4/B9 VBUS,5 A collective rating; all4GND contact identities retained",
"shell": "allold12S1..S4 B/T/TH logical shell aliases collapse to SH; no power orsignal net merge"
},
"sourceProvenance": {
"activeSourceSha256": "d756c1abfd3a83fb71e5070760b62ef7bbffecd5a90b1d34671eb2d9733faeb1",
"activePlacementSha256": "c2c3ea788936d0df2023374fa7196fdda1588c2affaa59b566437ff2fecbabfb"
}
}
]
}