hrithik18k/quad-sensor-conditioner

TSCIRCUIT-ISSUES.md

# New issues observed building Quad Sense

Date: 9 October 2026. Evidence is from this project's installed versions, not a claim about every upstream revision. No GitHub issues or PRs were created. P1/P2 are suggested priorities.

Excluded: previous invalid-selector/netlist behavior, SOIC package dimensions, dependency-version drift, legacy-router acceptance, replay warning wording, undefined-property inheritance, and related variants. Design mistakes (courtyard collision, capacitor orientation, over-spread schematic) were corrected and are not counted as platform issues.

| ID | Priority | Finding | Primary repository | Supporting repository |
| --- | --- | --- | --- | --- |
| Q1 | P1 | Ordinary through-hole pins receive top and bottom stencil paste by default | [core](https://github.com/tscircuit/core) | [props](https://github.com/tscircuit/props), [circuit-json-to-gerber](https://github.com/tscircuit/circuit-json-to-gerber) |
| Q2 | P1 | Gerber ZIP BOM loses an explicitly supplied manufacturer part number | [circuit-json-to-bom-csv](https://github.com/tscircuit/circuit-json-to-bom-csv) | [cli](https://github.com/tscircuit/cli) integration |
| Q3 | P2 | Pipeline9 throws on non-finite bounds during a partial check | [tscircuit-autorouter](https://github.com/tscircuit/tscircuit-autorouter) | [core](https://github.com/tscircuit/core); producer ownership still needs isolation |
| Q4 | P2 | Relative export destination resolves below the input directory, causing surprising ENOENT | [cli](https://github.com/tscircuit/cli) | export command documentation/tests |

## Q1 — Through-hole stencil paste

Observed in core 0.0.2116. Final Circuit JSON has 44 plated holes, 48 SMT pads, and 108 paste entries. Sixty paste entries have no pcb_smtpad_id and coincide with through-hole pins. There are 30 bottom-side paste apertures although the board has no bottom-side SMT components. The unmodified Gerber export has 78 F.Paste flashes and 30 B.Paste flashes.

Evidence: dist/index/circuit.json, dist/quad-sense-gerbers.zip. In core's PlatedHole implementation, the circular-hole branch unconditionally inserts top and bottom `pcb_solder_paste` records using the outer pad radius. This is not generated by footprinter. Other plated-hole shapes produce different paste behavior, so only some of the 44 holes appear in the paste output.

Expected: conventional through-hole components should not get stencil paste by default. Pin-in-paste should be explicit and configurable per layer/geometry. A solder-mask option is not a solder-paste option.

First fix: core plus tests for circular and rectangular plated pads, with props support if an opt-in is added. Gerber currently faithfully exports the bad input; do not suppress every THT aperture there because deliberate pin-in-paste may be valid.

Workaround supplied: scripts/prepare-fabrication.py removes the 60 unreferenced paste entries for this particular design; corrected export has 48 top apertures and zero bottom apertures. Copper is unchanged and passes short checks. Source/regenerated raw artifacts still exhibit the issue.

## Q2 — Explicit chip MPN lost from exported BOM

Source U1 specifies `manufacturerPartNumber="MCP6004-I/P"`. The emitted source_component retains `manufacturer_part_number: "MCP6004-I/P"`. However, the Gerber ZIP's bom.csv contains `"U1","","","dip14_w7.62mm"`: neither Comment nor Value identifies the IC. A DIP-14 footprint alone does not identify the component to buy.

Reproduce: build index.circuit.tsx; export its circuit.json using `tsci export ... -f gerbers`; inspect U1 in the ZIP BOM and compare to the source_component.

The CLI calls `convertCircuitJsonToBomRows({ circuitJson })` without a resolver. The bundled converter creates MPN comments from resolver-provided manufacturer_mpn_pairs but does not fall back to source_component.manufacturer_part_number. This is confirmed code-path evidence, not a parts-engine connectivity guess.

First fix: converter regression using a simple_chip with an explicit MPN and no resolver. Preserve resolver precedence, passive values, supplier columns and CSV escaping. Add CLI export integration coverage. The corrected fabrication ZIP includes an explicit assembly BOM generated from source metadata.

## Q3 — Non-finite solver bounds during partial rendering

`check schematic-placement` with the original auto_local source produced:
`ExpandEdgesToEmptySpaceSolver bounds must be finite, got {"minX":null,"maxX":null,"minY":null,"maxY":null}`
under `AutoroutingPipelineSolver9_PreloadedTraceGraph`, capacity-autorouter 0.0.958.

Evidence: evidence/schematic-placement-current.log, evidence/netlist-final.log from the earlier run was subsequently replaced by successful validation; the original source is retained at evidence/pipeline9-board.tsx. That source is a reproduction candidate, not a minimized standalone solver fixture.

A normal PCB build did succeed with pipeline9 after placement was corrected; therefore this is NOT evidence that pipeline9 cannot route this board. The final source selects beta_pipeline7, which built 69 traces with zero routing errors and passed partial checks. The exception may originate from running the router on an incomplete partial-render input. Isolate the input before assigning the final fix to the solver versus core. First contribution should be a minimized failing regression/repro, then reject/avoid invalid input or correct upstream bounds.

## Q4 — Relative output path surprise

Command from the project root:
`tsci export dist/index/circuit.json -f kicad_pcb -o evidence/initial.kicad_pcb`

The project-root evidence directory exists, but export attempted `dist/index/evidence/initial.kicad_pcb` and printed ENOENT. Evidence: evidence/kicad-initial.log. Using an absolute output path succeeds.

First verify the intended path contract; if input-relative destinations are deliberate, improve help/error text. Otherwise resolve explicit -o relative to the working directory and add a nested-input regression test. Do not silently change established semantics without maintainer agreement. This is a workflow/documentation issue, not a corrupt KiCad file.

## Other observations and ecosystem coverage

- Core reference-designator diagnostics say `RI1 ... should start with R` despite RI1 starting with R. The actual convention requires R followed by digits. Low-priority wording improvement; renamed parts to conventional R11/R21 etc. Evidence: evidence/build.log. Not a separate high-priority defect.
- React emits a special-key warning with keyed traces. No impact was isolated; not promoted to a confirmed issue.
- Audited footprinter, circuit-to-svg, circuit-json-to-gltf, KiCad export, Gerber export, BOM conversion, placement analysis, shorts checks and the router. No independent new defect was confirmed in the SVG/GLB/KiCad converters; a temporary via-count mismatch was caused by comparing exports from different builds and is excluded.
- Missing MPNs for generic passives and unverified supplier pick-and-place rotations are expected limitations of this design, not platform bugs.
- Init initially failed automatic dependency installation; explicit bun install succeeded. Not reported because it overlaps the previous dependency/toolchain issue family.