MustafaMulla29/rp2040-bldc-motor-controller-new

docs/validation.md

# Configurable-PD trial validation — 16 October 2026

The active trial reports are identified in `manufacturing/CURRENT-REVISION.md`. The review below describes the earlier 9 V baseline; its counts are historical and do not certify the changed PCB. Existing schematic style exceptions remain applicable where unchanged.

## Current trial schematic review

The new U12 ideal-diode controller has explicitly spaced right-side pins; its
box-padding warning is resolved without shrinking its three-pin left side.
The current native analyzer reports **16 style suggestions**: the 17 reviewed
baseline suggestions below, minus the removed D3. No new schematic placement
suggestions remain. The strict `bun run check` command still exits nonzero
because it treats every suggestion as a failure; that checker was not changed
or suppressed. The separate native PCB placement check has zero errors and
warnings. This is a reviewed-exceptions result, not an all-green aggregate run.

## Historical baseline review

# Compact PD-only board validation

The main build uses the saved-routing guard. Native netlist, PCB placement and full build completed; native PCB DRC has zero errors. Independent checks found no disconnected nets, floating copper or manufacturing-clearance findings. All 88 specified power/gate/bypass and parallel-via paths and 526 pad anchors pass. The current SHA and measurements are in `assembly/dist/results/pcb-validation.json`.

Both TypeScript projects typecheck. Seven firmware-policy/NVM tests and ten assembly tests pass. Firmware tests do not run hardware. Nine native schematic sheets render, with zero electrical wires crossing component symbol interiors.

## Schematic analysis review — 14 October

The installed CLI (`0.1.2198`, core `0.0.2021`) reproduced **20 schematic
placement suggestions**, both from the current source and the saved circuit
JSON. The reported UI count of 22 was not reproduced by this version.

Corrections in the schematic source:

- C40–C45, C49, C51–C53 now form two compact, vertical, five-capacitor rows.
  Native sections give each row clear power/ground rails without crossing wires.
  Notes identify the I/O, regulator, USB, bulk and flash bypass functions and
  retain the voltage ratings, while individual labels show capacitance.
- U3 is shorter with VIN/EN spaced to suit its box; U11's top pins are spread
  within its existing box. Both padding suggestions are resolved.
- U7's width is reduced from 2.24 to 2.00 schematic units; U5's height from
  10.88 to 10.72. Necessary clearance around the other pin labels is retained.
- D7 is rotated so its cathode faces the bias node and its anode faces ground.
  This removes the confusing reversed schematic orientation; its electrical
  connections and physical PCB orientation are unchanged.

The raw analyzer still reports **17 suggestions**, retained without suppressing
or editing checker output:

| Suggestions | Count | Reviewed disposition |
| --- | ---: | --- |
| J1/J19 box width | 2 | Native USB-C symbols need room for their connector glyph and pin labels. The suggested 1.15-wide box does not reserve that space. |
| U1/U5/U7 box height | 3 | Opposite sides have different pin counts/grouping. Shrinking for the shorter side crowds the longer side or its top/bottom labels; trial renders confirmed label collisions. |
| D1/R4 and D7/R141 alignment | 4 | These are parallel clamp/resistor pairs, not series chains. Their branches are intentionally drawn side by side. |
| D2/D5, D3, F1 and R13 vertical orientation | 5 | These are series supply isolation, fuse and current-sense components. Horizontal orientation preserves left-to-right power flow. |
| R93/R97/R101 flipping | 3 | The existing orientation puts each MOSFET gate above its return. Suggestions arise from individual branches of the shared return, including another phase, and would obscure the repeated half-bridge layout. |

The strict aggregate checker is therefore not warning-free. There are no
remaining component/text overlaps, inner-label collisions, capacitor grouping
findings, or electrical wires crossing IC/connector interiors in the final
schematic analysis/render. All labels remain generated from net connections;
no manual netlabels were added. This schematic review is not hardware or
manufacturing approval.

## Test-pad courtyard review — 13 October

All 16 exposed 1.5 mm test pads now have native 2.5 mm diameter top-side
courtyards (0.5 mm beyond the copper edge), matching the geometry of
[KiCad's D1.5 mm test-pad footprint](https://github.com/KiCad/kicad-footprints/blob/master/TestPoint.pretty/TestPoint_Pad_D1.5mm.kicad_mod).
Courtyards reserve placement/probe space; they are not extra copper or silkscreen.
The pads still have 1.6 mm solder-mask openings and no solder paste. They require
no purchased test-point parts and do not enter the assembled BOM or CPL.

The larger probe envelopes exposed tight component clearance. TP4/TP5 move
0.515 mm upward, TP11–TP14 move 0.05 mm left, R133 moves 0.24 mm left and R143
moves 0.25 mm upward. Their local trace branches and two existing signal vias
are adjusted. The outline remains 73 × 72 mm, with 475 vias and 152 fitted parts.
Main motor power paths, the Kelvin pair, schematic and electrical connections are
unchanged. Trace widths are retained.

All 168 courtyards (152 fitted parts plus 16 probe pads) and mounting screw
clearances pass. Native placement reports zero errors and warnings; native PCB
DRC reports zero errors and **19 remaining custom-symbol/import-model warnings**.
The 16 missing-courtyard warnings are resolved in the source footprints, without
suppressing checks. Raw build output has 23 warnings including the four previously
documented wrapper/synthetic-pin advisories.

Independent copper connectivity/clearance, all 88 configured width paths,
Kelvin sensing, via cleanup and 526 pad anchors pass. The saved-routing guard
remains enabled. The integrated assembly and factory-review exports are rebuilt
from the current board; hardware-release holds in [order readiness](order-readiness.md)
remain open. Current measurements are in
`assembly/dist/results/testpad-courtyard-review.json`.

## Schematic readability review — 12 October, second pass

The eight circuit pages now use A4 landscape instead of ANSI B, with closer
functional groups and unchanged-size electrical symbols. This makes symbol and
pin text about 40% larger relative to the page. The connection guide retains its
larger overview page. Decoupling banks, test pads, transistor bias resistors and
captions have explicit spacing. The crystal is drawn as a resonator with its
case grounds below the signal path; its frequency/load specification is visible.
The bridge has identical, labelled U/V/W columns with MOSFET part names. PD
pull-ups use a separate local bank and generated named connections instead of
long crossing wires around the controller. No manual netlabels are authored.

Layout references reviewed online:

- [STUSB4500 datasheet, Figure 10](https://www.st.com/resource/en/datasheet/stusb4500.pdf): USB connector, negotiation controller and switched power path.
- [RP2040 minimal design, Figure 11](https://datasheets.raspberrypi.com/rp2040/hardware-design-with-rp2040.pdf): local crystal/flash networks and separate supply bypass banks.
- [TI MCT8329EVM, Figures 8-5 and 8-7](https://www.ti.com/lit/ug/sllu359a/sllu359a.pdf): grouped gate-driver supplies, bootstrap circuits and user controls.

### Corrections to warnings

Fresh native warnings fall from **72 to 35**:

- Q10–Q15 now use native `mosfet`; Q5/Q6 use `transistor`; RV1 uses
  `potentiometer` with its 10k value and deliberately unconnected mounting tabs;
  J10–J12 use `connector`. All retain their actual pin numbers, footprints,
  supplier parts and CAD models. These correct component types remove 35
  inappropriate chip-only power/ground/pin-role warnings.
- Q1/Q2's gate terminals explicitly require a connection. This is a real device
  requirement and removes the two remaining underspecified-pin warnings.
- Caption/net-label collisions and component overlap introduced by the tighter
  layout were resolved in source and checked again. No generated warning records
  or third-party checkers were edited, suppressed or filtered.

### Warnings remaining after the 12 October review (historical)

| Warning | Count | Finding |
| --- | ---: | --- |
| Missing component courtyard | 16 | Resolved by the 13 October review above: all bare probe pads now have explicit courtyards and checked access clearance. |
| Custom symbol missing reference text | 14 | SW4, Q1/Q2, U10, Y1, Q5/Q6, RV1 and Q10–Q15 all have visible, correctly named text. The pinned checker searches inside the custom symbol's body bounds and misses conventional adjacent captions. |
| No IC power pin | 3 | Q1/Q2 are eight-terminal PMOS packages and Y1 is a passive crystal. Their retained imported chip wrappers trigger an IC-only rule. These parts do not have IC supply terminals to declare. |
| No IC ground pin | 2 | Q1/Q2 have source, drain and gate terminals; none is a permanent ground pin. Declaring one as ground would be incorrect. |

The raw build also contains three wrapper reference-prefix advisories for
Q1/Q2/Y1 and the existing synthetic SW4 `pin4` advisory: **39 raw warnings**.
The actual C&K switch has pins 1/2/3/5/6/7; pin4 has no physical land or custom
symbol terminal. No real switch pin is omitted or changed.

Native schematic-placement checking finds no component overlap, text collision,
net-label collision or inner-label collision. Its general style suggestions
still include asymmetric IC pin banks, horizontal series power parts, parallel
clamp/resistor pairs and grouping all same-rail decouplers despite their different
functions. They are retained where the suggestion would obscure the circuit.
The strict aggregate checker is therefore **not claimed to be warning-free**.

### Preservation and verification

The 571 pin identities/net mappings, 97 nets, 492 electrical trace connections and
8 internal connections are unchanged. Eighteen source trace descriptions now use
numbered MOSFET selectors in place of equivalent G/D/S aliases. All 4,693 PCB
geometry/copper records are unchanged; native connectors additionally emit their
cable-insertion metadata. The assembly asset and provenance were regenerated
through the existing build pipeline; the mechanical GLB remains byte-identical.

The saved-routing guard, TypeScript check, native PCB DRC, independent copper
connectivity/clearance, all 88 width paths, Kelvin pair, route cleanup, 152 fitted
courtyards and 526 pad anchors pass. All nine sheets are rendered and visually
reviewed. Native schematic wiring has no component-interior crossings. Package
integration compares the PCB, schematic and connectivity against the PCB-only
build, and all ten assembly tests pass. These schematic improvements do not clear the hardware-release hold in
[order readiness](order-readiness.md).

## Integrated package assembly — 9 October

`system.circuit.tsx` renders the live PCB together with the motor, three original leads, three rigid adapters and two USB cables in the standard `tsci dev` 3D viewer. The mechanical GLB contains no PCB. All 46 board, circuit and import source files stayed unchanged during integration; the integrated build preserves the PCB records, schematic and electrical connectivity.

The complete authoring/build pipeline, both TypeScript checks and ten assembly tests passed. Native PCB DRC and the independent connectivity/clearance audits reported zero findings. Existing schematic/style advisories remain for the deferred schematic work; the strict aggregate checker is not claimed to pass.

A separate portable package copy, excluding the local `assembly/` authoring tools and generated files, also completed `bun run build` and its integration check. The standard viewer was visually inspected on the main project. This verifies local rendering and a portable package build; the package has not been published as part of this change. CAD visualization does not establish physical connector fit; dimensional limitations remain documented in [full assembly](full-assembly.md).

The second via/placement pass reaches **473 vias**. Five unnecessary signal vias
and unused tails were removed; all ground/power/gate-drive vias remain. C2/C3
now follow the PD regulator pin order, using two direct top-layer bypass paths.
The layout audit enforces their length/layer/width/anchors and all 152 component
courtyards; the width audit contains 71 required paths. Electrical net/pin mapping
and all other component placements remain unchanged.

The third pass retains **473 vias**, rechecks all 152 component courtyards and
widens the remaining reviewed local supply/charge-pump branches to at least
0.20 mm. C48 takes the nearer VREG_OUT capacitor position; one retained ground
via shifts 0.25 mm to clear the wider core trace. There are now **80** required
physical width paths. The cleanup audit covers six complete local supply rails,
not only 3.3 V. See the third-pass table in [routing review](routing.md).

The fourth review validates the **73 × 74 mm** outline. It retains 473 vias and
all reviewed trace widths; C140 is closer to the power-switch IC. The width
audit now checks **82 paths** and the existing 526 pad anchors. Native DRC,
physical connectivity, clearance, unused-via and all 152 courtyard checks pass.
The integrated assembly is regenerated for the moved socket positions and its
reported board size is read from the compiled PCB geometry.


The fifth review validates **73 × 73 mm** with 473 vias, **88** specified width
paths, 526 pad anchors and all 152 fitted-component courtyards/screw envelopes.
Native PCB DRC and the independent physical connectivity/clearance checks have
zero findings. All 173 individually tested signal/control vias are necessary
for the retained copper. Ground/thermal and paired-power vias remain.
The assembly derives its connector frames and board size from the compiled PCB.
See [compact layout](compact-layout.md) for placement and routing measurements.


The sixth review (12 October) is **73 × 72 mm**, with 12 moved component/test-pad
placements and unchanged main power routing. Eight existing routing vias move;
two LED signal transitions bring the total to **475**. The ground-reference
layer remains free of non-ground traces. All 22 explicit
ground/thermal vias and 42 parallel power-via pairs remain. All 88 width paths,
526 pad anchors and 152 courtyards/screw envelopes pass. The expanded whole-rail
scan checks 11 local supplies with no thin branches. All 175 tested signal/control
vias are necessary for retained copper connectivity. See [compact layout](compact-layout.md)
for measured routing tradeoffs and the updated hole positions.


## 14 October 2026 — native U7 solder-paste windows

The PCB runtime is pinned to core 0.0.2153 and props 0.0.702 with the matching
runtime schema/helper releases in package.json. The existing CLI/upload patch and
saved routing remain intact. New-core compatibility uses `routeRemaining` to
invoke the saved router and `doNotPlace` for the 16 bare probe pads; no physical
component was removed. The routing-input guard passed without changes to its
reference or saved traces.

U7 pad 37 remains one continuous 3.6500054 × 2.6500074 mm copper land.
`solderPasteMargin={-2}` removes only its automatic opening. Six native
`<solderpaste shape="rect">` elements produce 1.05 × 1.15 mm windows at the
specified centers. `check-native-stencil.mjs` checks the **unmodified native
F_Paste Gerber** and requires exactly six correctly sized/positioned flashes,
six independent native paste records, unchanged copper dimensions and the
unchanged U11 opening. The native preview is generated from those parsed flashes.
The six rectangular windows cover 74.90% of the land. R0.05 corner rounding in
the factory drawing is still a process request, not a supported native prop;
its rounded area is 74.77%. No new core patch, fake copper or Gerber rewrite is used.

The newer core also supplies previously absent pill-pad paste records for
U1/U11/Q1/Q2/U6 and stops generating paste on ordinary through-hole-only parts.
The native export now has 502 top flashes and 8 bottom USB-shell-slot flashes.
Those shell slots still need the documented separate THT process; the raw paste
files do not authorize pin-in-paste or bottom-side assembly.

Exact comparison with the pre-update build confirms unchanged board outline,
copper pads, traces, vias, pours, masks, courtyards and silkscreen. Source nets,
traces and internal connections are unchanged. Source-port changes are only
new input/output/passive metadata. New-core schematic wire routing is regenerated;
the same 17 reviewed schematic style advisories remain, with no wire crossing
through any of the 12 IC boxes. Native PCB placement reports no issues.
All seven independent PCB audit groups pass, including the 88 width paths,
Kelvin sensing and 526 pad anchors. The new checker reports 51 non-45-degree
trace-style advisories on existing unchanged routes, plus five existing
power/ground pin-metadata warnings. These are recorded, not suppressed; this
paste update does not straighten or reroute copper.

The assembly is rebuilt through its existing pipeline. Its external mechanical
asset remains unchanged; provenance and the integrated system build are refreshed
to match the new native PCB records. This revision closes the missing-six-windows
export issue, not factory approval or the remaining hardware/firmware qualification
items in order-readiness.md.