MustafaMulla29/rp2040-bldc-motor-controller-new

circuit/routing-plan.tsx

import { Fragment } from "react"

const powerNets = ["PD9_FUSED", "PD_LOAD", "VBUS_RAW", "PD_SWITCHED", "PD9", "LOGIC_IN", "VMOTOR", "V3V3", "V1V1", "ADC_AVDD", "PD_2V7", "PD_1V2", "MCT_AVDD", "MCT_DVDD", "MCT_GVDD"]
const motorNets = new Set(["PD9_FUSED", "PD_LOAD", "GND", "VMOTOR", "LS_RETURN", "PHASE_U", "PHASE_V", "PHASE_W"])
const pdNets = new Set(["VBUS_RAW", "PD_COMMON_S", "PD_SWITCHED", "PD9", ])
const logicNets = new Set(["V3V3", "V1V1", "LOGIC_IN", "LOGIC_SW"])
// Net metadata and widths only. The default router solves all nets together.
const names = ["PD9_FUSED", "PD_LOAD", "POWER_ON_LEVEL", "POWER_SWITCH_EN", "POWER_CURRENT_LIMIT","PROG_VBUS", "PROG_CC1", "PROG_CC2", "PROG_PRESENT", "VBUS_RAW", "PD_SWITCHED", "PD9", "LOGIC_IN", "VMOTOR", "V3V3", "V1V1", "ADC_AVDD", "PD_2V7", "PD_1V2", "MCT_AVDD", "MCT_DVDD", "MCT_GVDD", "GND", "LS_RETURN", "PHASE_U", "PHASE_V", "PHASE_W", "PD_COMMON_S", "LOGIC_SW", "MCT_CPL", "MCT_CPH", "MCT_BSTA", "USB_DP", "USB_DM", "MCU_USB_DP", "MCU_USB_DM", "XIN", "XOUT", "XTAL_OUT", "QSPI_SS", "QSPI_SCLK", "QSPI_SD0", "QSPI_SD1", "QSPI_SD2", "QSPI_SD3", "BOOTSEL", "SWDIO", "SWCLK", "RUN", "CC1", "CC2", "PD_RESET", "PD_SCL", "PD_SDA", "PD_DISCH", "PD_ATTACH_N", "PD_OK2_N", "PD_SNK_EN", "PD_VS", "PD_ALERT_N", "PD_GATE", "IIN_RAW", "ADC_VBUS", "ADC_IIN", "LOGIC_BST", "ADC_VMOTOR", "MCT_SDA", "MCT_SCL", "MOTOR_SPEED", "MOTOR_ARM", "MOTOR_FAULT_N", "MOTOR_FG", "ARM_REQUEST_N", "STATUS_LED", "ADC_THROTTLE", "LED_A", "GHA", "GLA", "MCT_BSTB", "GHB", "GLB", "MCT_BSTC", "GHC", "GLC", "MCT_DRVOFF", "MCT_DIR", "MCT_EXTCLK", "MCT_BRAKE", "PD_INHIBIT_B", "ARM_BASE", "THROTTLE_IN", "GHA_GATE", "GLA_GATE", "GHB_GATE", "GLB_GATE", "GHC_GATE", "GLC_GATE", "IDEAL_GATE", "IDEAL_VCAP", ]

/** Native router constraints. Widths are design targets, not current ratings.
 * Actual routed neck-downs/returns still require inspection before fabrication.
 */
export function RoutingPlan() {
  return <>
    {/* A native routing phase keeps authored pcbPath copper fixed. */}
    {/* Routing guard bands exceed the board's 0.10 / 0.10 / 0.30 mm checks. */}
    {names.map(name => <Fragment key={name}>
      <net name={name} isGroundNet={name === "GND"}
        
        isPowerNet={powerNets.includes(name)}
        nominalTraceWidth={motorNets.has(name) ? 2 : pdNets.has(name) ? 1 : logicNets.has(name) ? 0.3 : undefined} />
    </Fragment>)}
  </>
}