0hmX/am3352-ddr-track-c-stackup-wip-20261007
Saved native stackup-first preview: 11 DDR endpoint routes and 179 selected pad-to-plane joins. Matching and full-board connectivity incomplete. Not fabrication-ready.
- Version
- 0.0.2
- License
- unset
- Stars
- 0
index.tsx
import { AM3352 } from "./components/AM3352"
import { W631GG6MB_12 } from "./imports/W631GG6MB_12"
import { cpuConnections, ramConnections, ddrSignals } from "./connections"
import { DdrRouting } from "./routing"
import { ReferencePlanes } from "./planes"
import { Support } from "./support"
import { Byte0Escapes } from "./escapes"
import { PlaneFeeds } from "./plane-feeds"
// Core has no physical stackup prop. See evidence/jlc-standard-stackups.json.
export default function Board({ routeDdr = false, ddrOnly = false, planes = false, byte0Only = false, escapePreview = false, savedByte = false } = {}) {
// Signal traces own these nets. Duplicate automatic net traces make pair cohorts ambiguous.
const signalNets = new Set(ddrSignals.map(signal => `net.${signal.net}`))
const withoutSignals = (connections: Record<string, string>) => Object.fromEntries(
Object.entries(connections).filter(([, net]) => !signalNets.has(net)))
return <board width={ddrOnly ? 45 : 106} height={ddrOnly ? 48 : 70}
outline={ddrOnly ? undefined : [{x:-28,y:32},{x:78,y:32},{x:78,y:-38},{x:-28,y:-38}]}
layers={8} thickness={1.2} doubleSidedAssembly
routingDisabled={!routeDdr && !savedByte} routeRemaining={false}
allowBlindAndBuriedVias={false} schAutoLayoutEnabled={false}
minTraceWidth={0.1} minTraceToPadEdgeClearance={0.1}
minTraceToHoleEdgeClearance={0.2}
minPadEdgeToPadEdgeClearance={0.15} minViaEdgeToPadEdgeClearance={0.1}
minViaHoleEdgeToViaHoleEdgeClearance={0.2}
minViaHoleDiameter={0.2} minViaPadDiameter={0.45}
title="Track C — standard eight-layer stackup study; unqualified">
<AM3352 name="U1" pcbX={0} pcbY={4} connections={withoutSignals(cpuConnections)} noSchematicRepresentation />
<W631GG6MB_12 name="U3" pcbX={0} pcbY={-17} pcbRotation={270}
connections={withoutSignals(ramConnections)} noSchematicRepresentation />
{!ddrOnly && <Support />}
<DdrRouting route={routeDdr} byte0Only={byte0Only} escapePreview={escapePreview} savedByte={savedByte} />
{escapePreview && <Byte0Escapes />}
{planes && <><PlaneFeeds /><ReferencePlanes /></>}
<pcbnotetext pcbX={21} pcbY={29} fontSize={0.8}
text="C: JLC08121H-3313 / 0.20-0.45 through vias / RELEASE BLOCKED" />
</board>
}