0hmX/am3352-ddr-track-b-byte0-wip-20261007

Partial full-board preview: 11 of 47 DDR signal nets routed; power and interfaces incomplete. Fabrication and electrical release blocked.

Version
0.0.1
License
unset
Stars
0

stackup.ts

import physical from "./contracts/physical-stackup.json"

// JLC live calculator: JLC08161H-2116. Physical order, top to bottom.
// No frequency-qualified Er/Df or impedance certification is inferred.
export const stackup = {
  name: physical.name, thicknessMm: physical.finishedNominalMm, thicknessTolerancePercent: physical.finishedTolerancePercent,
  copperMm: physical.copperMm,
  dielectricMm: physical.dielectricMm,
  roles: ["signal", "GND", "signal", "GND", "power", "signal", "GND", "signal"],
  outer50OhmWidthMm: 0.181356,
  l3SingleEnded50OhmWidthMm: 0.170688,
  outerDifferential100OhmWidthMm: 0.139192,
  outerDifferential100OhmEdgeGapMm: 0.2032,
  l3Differential100OhmWidthMm: 0.134874,
  l3Differential100OhmEdgeGapMm: 0.2032,
  differentialGapStatus: "Outer and L3 calculator geometry recorded; no measured impedance or SI qualification",
} as const

// Copper centroid depths for geometric route accounting only. Modal propagation,
// via stubs, package delay and material uncertainty need separate SI validation.
export const layerDepthsMm: Record<string, number> = {}
let copperTop = 0
physical.layers.forEach((layer, index) => {
  layerDepthsMm[layer] = copperTop + physical.copperMm[index]! / 2
  copperTop += physical.copperMm[index]! + (physical.dielectricMm[index] ?? 0)
})