0hmX/am3352-ddr-track-b-byte0-wip-20261007
Partial full-board preview: 11 of 47 DDR signal nets routed; power and interfaces incomplete. Fabrication and electrical release blocked.
- Version
- 0.0.1
- License
- unset
- Stars
- 0
planes.tsx
import { Fragment } from "react"
// Prospective references. Actual connection/coverage is checked after fill and routing.
// The pour solver expects the same counterclockwise winding as board outlines.
export const ddrRegion = [{ x: -30, y: -17 }, { x: -6, y: -17 }, { x: -6, y: 13 }, { x: -30, y: 13 }]
// New byte candidate extends past the earlier L5 edge; preserve the old region.
export const byte0DdrRegion = [{ x: -30, y: -17 }, { x: -4, y: -17 }, { x: -4, y: 14 }, { x: -30, y: 14 }]
export function ReferencePlanes({ region = ddrRegion }: { region?: typeof ddrRegion } = {}) {
return <>
{(["inner1", "inner3", "inner6"] as const).map(layer => <Fragment key={layer}>
<copperpour name={`GND_${layer}`} layer={layer} connectsTo="net.GND"
clearance={0.11} boardEdgeMargin={0.5} unbroken useThermalReliefs={false} />
</Fragment>)}
<copperpour name="DDR1V5_L5" layer="inner4" connectsTo="net.DDR_1V5"
outline={region} clearance={0.11} unbroken useThermalReliefs={false} />
</>
}