0hmX/am3352-ddr-track-b-byte0-wip-20261007

index.tsx

import { Cpu, DdrMemory } from "./bga"
import cpuNets from "./contracts/cpu-nets.json"
import { ddrConnections, ramConnections, ramNoConnect } from "./ddr-nets"
import { DdrRouting } from "./ddr-routing"
import { Support } from "./support"
import { stackup } from "./stackup"
import { SavedByte0Routing, savedByte0Nets } from "./saved-byte0"
import { ReferencePlanes, byte0DdrRegion } from "./planes"
import { PmicThermalVias } from "./pmic-footprint"
import { SavedDqRouting, savedDqNets, DdrPlaneFeed } from "./saved-dq"
import matchedDqPaths from "./contracts/matched-dq-paths.json"

export default function Board({ routeDdr = false, ddrOnly = false, byte0Only = false, savedDq = false, matchedDq = false, savedByte0 = false }: { routeDdr?: boolean; ddrOnly?: boolean; byte0Only?: boolean; savedDq?: boolean; matchedDq?: boolean; savedByte0?: boolean } = {}) {
  savedDq ||= matchedDq || savedByte0
  const ownedDdrNets = routeDdr ? new Set(ddrConnections.map(connection => connection.net)) : savedByte0 ? savedByte0Nets : savedDqNets
  const cpuConnections = Object.fromEntries(Object.entries(cpuNets)
    .filter(([, net]) => !(routeDdr || savedDq) || !ownedDdrNets.has(net)).map(([ball, net]) => [ball, `net.${net}`]))
  const memoryConnections = Object.fromEntries(Object.entries(ramConnections)
    .filter(([, net]) => !(routeDdr || savedDq) || !ownedDdrNets.has(net.slice(4))))
  return <board width={110} height={100} layers={8} thickness={stackup.thicknessMm}
    title="AM3352 track B — placement and DDR routing study; release gates open"
    doubleSidedAssembly routingDisabled={!routeDdr} routeRemaining={false} schAutoLayoutEnabled={false}
    minTraceWidth={0.1016} minPadEdgeToPadEdgeClearance={0.15} minTraceToPadEdgeClearance={0.1} minTraceToHoleEdgeClearance={0.2}
    minViaPadDiameter={0.4} minViaHoleDiameter={0.2}
    pcbStyle={{ viaPadDiameter: 0.4, viaHoleDiameter: 0.2 }}>
    <Cpu name="U_CPU" pcbX={-18} pcbY={15} noSchematicRepresentation
      connections={ddrOnly ? undefined : cpuConnections} />
    <DdrMemory name="U_DDR" pcbX={-18} pcbY={-8} pcbRotation={270} noSchematicRepresentation
      connections={ddrOnly ? undefined : memoryConnections} noConnect={ramNoConnect} />
    {routeDdr && <DdrRouting byte0Only={byte0Only} />}
    {savedDq && <>{savedByte0 ? <SavedByte0Routing /> : <SavedDqRouting paths={matchedDq ? matchedDqPaths : undefined} />}<DdrPlaneFeed /></>}
    {matchedDq && !savedByte0 && <bus name="SAVED_DDR_BYTE0" connections={matchedDqPaths.map(path => `SAVED_${path.net}`)}
      maxLengthSkew={0.635} pcbTraceWidth={stackup.l3SingleEnded50OhmWidthMm} pcbAllowedLayers={["inner2"]} />}
    {!ddrOnly && <Support byte0={savedByte0} />}
    {!ddrOnly && <PmicThermalVias x={15} y={26} />}
    {!ddrOnly && <ReferencePlanes region={savedByte0 ? byte0DdrRegion : undefined} />}
    <pcbnotetext pcbX={-18} pcbY={-19} text="DDR keepout: continuous GND references, L5 DDR1V5 plane required" fontSize={0.8} />
    <pcbnotetext pcbX={0} pcbY={47} text="TRACK B  |  JLC08161H-2116  |  RESEARCH / NOT FOR FABRICATION" fontSize={0.9} />
  </board>
}