0hmX/am3352-ddr-track-b-byte0-wip-20261007

ddr-routing.tsx

import { Fragment } from "react"
import { ddrConnections } from "./ddr-nets"
import { stackup } from "./stackup"

const cpuPort = (net: string) => {
  const connection = ddrConnections.find(connection => connection.net === net)
  if (!connection) throw new Error(`Missing DDR signal ${net}`)
  return `.U_CPU > .${connection.cpuBall}`
}

export function DdrRouting({ byte0Only = false }: { byte0Only?: boolean }) {
  const byteData = (byte: number) => [
    ...Array.from({ length: 8 }, (_, bit) => `DDR_D${byte * 8 + bit}`), `DDR_DQM${byte}`,
  ]
  const byteNets = (byte: number) => [...byteData(byte), `DDR_DQS${byte}`, `DDR_DQSn${byte}`]
  const byteMembers = [...byteNets(0), ...byteNets(1)]
  const addressNets = ddrConnections.map(connection => connection.net).filter(net =>
    !byteMembers.includes(net) && !["DDR_RESETn", "DDR_CK", "DDR_CKn"].includes(net))
  const connections = byte0Only ? ddrConnections.filter(connection => byteNets(0).includes(connection.net)) : ddrConnections
  return <>
    <autoroutingphase name="DDR_LANES" phaseIndex={1} autorouter="bus_lanes" />
    {connections.map(connection => <net name={connection.net} routingPhaseIndex={1} />)}
    {connections.map(connection => <trace key={connection.net} name={`T_${connection.net}`} routingPhaseIndex={1}
      path={[cpuPort(connection.net), `.U_DDR > .${connection.ramBall}`, `net.${connection.net}`]} />)}
    {/* Core 0.0.2097 does not forward props lengthMatchTo. Matching data to
        DQS, and address/control to CK, requires an independent actual-route
        check; accepting the prop would not enforce that requirement. */}
    {(byte0Only ? [0] : [0, 1]).map(byte => <Fragment key={byte}>
      <bus name={`DDR_BYTE${byte}`} routingPhaseIndex={1} connections={byteData(byte).map(cpuPort)}
        maxLengthSkew={0.635}
        pcbTraceWidth={byte === 0 ? stackup.l3SingleEnded50OhmWidthMm : stackup.outer50OhmWidthMm}
        targetImpedance={50} pcbTraceSpacing="3w" pcbSpacingToOtherSignals="4w"
        pcbAllowedLayers={[byte === 0 ? "inner2" : "bottom"]} />
      <bus name={`DDR_DQS_CARRIER${byte}`} routingPhaseIndex={1}
        connections={[`DDR_DQS${byte}`, `DDR_DQSn${byte}`].map(cpuPort)}
        pcbTraceWidth={byte === 0 ? stackup.l3Differential100OhmWidthMm : stackup.outerDifferential100OhmWidthMm}
        pcbAllowedLayers={[byte === 0 ? "inner2" : "bottom"]} />
      <differentialpair name={`DDR_DQS_PAIR${byte}`} positiveConnection={cpuPort(`DDR_DQS${byte}`)}
        negativeConnection={cpuPort(`DDR_DQSn${byte}`)} maxLengthSkew={0.127}
        targetDifferentialImpedance={100} pcbTraceGap={0.2032} pcbSpacingToOtherSignals="4w" />
    </Fragment>)}
    {!byte0Only && <>
      <bus name="DDR_ADDRESS_CONTROL" routingPhaseIndex={1} connections={addressNets.map(cpuPort)}
        maxLengthSkew={0.635} pcbTraceWidth={stackup.outer50OhmWidthMm}
        targetImpedance={50} pcbTraceSpacing="3w" pcbSpacingToOtherSignals="4w" pcbAllowedLayers={["top"]} />
      <bus name="DDR_CLOCK_CARRIER" routingPhaseIndex={1} connections={["DDR_CK", "DDR_CKn"].map(cpuPort)}
        pcbTraceWidth={stackup.outerDifferential100OhmWidthMm} pcbAllowedLayers={["top"]} />
      <differentialpair name="DDR_CLOCK" positiveConnection={cpuPort("DDR_CK")} negativeConnection={cpuPort("DDR_CKn")}
        targetDifferentialImpedance={100} maxLengthSkew={0.127} pcbTraceGap={0.2032} pcbSpacingToOtherSignals="4w" />
    </>}
  </>
}